ARM, RISC-V контроллеры

в одних камнях флаги ошибок приема сбрасываются автоматически при чтении регистра данных, в других нет - нужно сбрасывать программно 

RM0090

Status register (USART_SR)

ORE: Overrun error

This bit is set by hardware when the word currently being received in the shift register is

ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if

RXNEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the

USART_SR register followed by a read to the USART_DR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set, the RDR register content will not be lost but the shift register will be

overwritten. An interrupt is generated on ORE flag in case of Multi Buffer

communication if the EIE bit is set.