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evgeniy1294 (23.02.2021 00:15, просмотров: 21) в ответ на Блок-схема в даташите говорит, что да, без разницы. - автор: evgeniy1294
The L1-cache can be a performance booster when used in conjunction with memory interfaces on AXI bus. This must not be confused with memories on the Tightly Couple Memory (TCM) interface, which are not cacheable. Any normal memory area can be cacheable, as described above, but the biggest gains are seen on memories accessed by the AXI bus such as the internal Flash memory, internal SRAMs and external memories attached to the FMC or Quad-SPI controllers