ARM, RISC-V контроллеры

Пусть errata поживает. Конечно я могу прошуршать по-быстрому DS, RM, освежить свою пaмять и привести здесь характеристики, подвига в этом не будет. Там масса всяких моментов. Но вопрос у меня по "бомбовости" Renesas. Если именно в этом его бомба, ну, какая-то она не сильно ядрёная получается. :) STM32F756: The Flash memory has the following main features: • Capacity up to 1 Mbyte • 256 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase The Flash memory is organized as follows: • A main memory block divided into 4 sectors of 32 Kbytes, 1 sector of 128 Kbytes, and 3 sectors of 256 Kbytes • Information blocks containing: – System memory from which the device boots in System memory boot mode – 1024 OTP (one-time programmable) for user data – The OTP area contains 16 additional bytes used to lock the corresponding OTP data block. – Option bytes to configure read and write protection, BOR level, watchdog, boot memory base address, software/hardware and reset when the device is in Standby or Stop mode. The embedded flash has three main interfaces: • 64-bits ITCM interface: – It is connected to the ITCM bus of Cortex-M7 and used for instruction execution and data read access. – Write accesses are not supported on ITCM interface – Supports a unified 64 cache lines of 256 bits (ART accelerator) • 64-bits AHB interface: – It is connected to the AXI bus of Cortex-M7 through the AHB bus matrix and used for code execution, read and write accesses. – DMAs and peripherals DMAs data transfer on flash are supported only through the AHB interface. • 32-bits AHB register interface: – It is used for control and status register accesses.