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POV_ (13.06.2017 13:02, просмотров: 1) ответил POV_ на Ну вот по ссыли
Вот мне ответили в коммунити ADишного. Описано вполне ожидаемое поведение SPI. Однако что-то в консерватории не так (( 
When /CS is inactive, any activities on SPI lines will be ignored since the bus will be disabled. When /CS is held low or active, the ADC will then have access to the data bus between itself and the microprocessor. It is important that you provide the correct number of clock cycles when reading from or writing to the control registers. If you provide one extra clock cycle and then write to the part, you will put the part into an unexpected state.  A user can transmit the data as a continuous stream or the data can be split into bytes. For example, if writing 24 bits to the ADC, all 24 bits can be transmitted continuously or the data can be divided into 8-bit words. However, if the data is divided into bytes, /CS must be held low until all bytes are transmitted. Thus, "it is recommended that SCLK idles high between data transfers" means that SCLK should be idle high between the 8 bit reads. However, when using the /CS line as a Frame Sync, The SCLK can continue to run between data transfers, provided the timing numbers are obeyed meaning that this line is brought high at the correct time. Check  that you have allowed the correct number of clock pulses to occur before /CS is brough high.