ВходНаше всё Теги codebook 无线电组件 Поиск Опросы Закон Пятница
29 марта
885777 Топик полностью
Nikolay_Po (30.11.2018 22:53 - 22:55, просмотров: 339) ответил m16_home на радость была преждевременной
Вот, для PIC24HJ64GP202  Line Address Opcode Label DisAssy 1,071 085C 2003F1 Go40MIPS MOV #0x3F, W1 1,072 085E 200010 MOV #0x1, W0 1,073 0860 883A41 MOV W1, OSCTUN 1,074 0862 2009A2 MOV #0x9A, W2 1,075 0864 883A20 MOV W0, CLKDIV 1,076 0866 883A31 MOV W1, PLLFBD 1,077 0868 200781 MOV #0x78, W1 1,078 086A 207433 MOV #0x743, W3 1,079 086C 784981 MOV.B W1, [W3] 1,080 086E 784982 MOV.B W2, [W3] 1,081 0870 784980 MOV.B W0, [W3] 1,082 0872 803A12 MOV OSCCON, W2 1,083 0874 200571 MOV #0x57, W1 1,084 0876 A00002 BSET W2, #0 1,085 0878 200460 MOV #0x46, W0 1,086 087A 207423 MOV #0x742, W3 1,087 087C 784980 MOV.B W0, [W3] 1,088 087E 784981 MOV.B W1, [W3] 1,089 0880 784982 MOV.B W2, [W3] 1,090 0882 270002 MOV #0x7000, W2 1,091 0884 210001 MOV #0x1000, W1 1,092 0886 803A13 MOV OSCCON, W3 1,093 0888 610003 AND W2, W3, W0 1,094 088A 500F81 SUB W0, W1, [W15] 1,095 088C 3AFFFC BRA NZ, .L2 1,096 088E 200201 MOV #0x20, W1 1,097 0890 803A12 MOV OSCCON, W2 1,098 0892 608002 AND W1, W2, W0 1,099 0894 32FFFD BRA Z, .L4 1,100 0896 060000 RETURN Или !void Go40MIPS(void) { ! ! OSCTUN = ((unsigned)(OscTune)*(1<<10))>>10; 0x85C: MOV #0x3F, W1 0x860: MOV W1, OSCTUN ! ! //Using internal oscillator ! CLKDIV = 0 << _CLKDIV_ROI_POSITION //Don't clear DOZEN on interrupt 0x85E: MOV #0x1, W0 0x864: MOV W0, CLKDIV ! | 0b000 << _CLKDIV_DOZE_POSITION //Dose mode Fcy/1 (ineffective) ! | 0 << _CLKDIV_DOZEN_POSITION //Dose mode is off, CPU/peripheral 1:1 ! | 0b000 << _CLKDIV_FRCDIV_POSITION //FRC divide by 1 (none division) ! | 0b00 << _CLKDIV_PLLPOST_POSITION //1:2 PLL postscaler ! | (3-2) << _CLKDIV_PLLPRE_POSITION; //1:3 PLL prescaler ! PLLFBD = 65 - 2; //PLL feedback divisor 0x866: MOV W1, PLLFBD ! __builtin_write_OSCCONH(0b001); //Set new OSC for FRCDIVN+PLL 0x862: MOV #0x9A, W2 0x868: MOV #0x78, W1 0x86A: MOV #0x743, W3 0x86C: MOV.B W1, [W3] 0x86E: MOV.B W2, [W3] 0x870: MOV.B W0, [W3] ! __builtin_write_OSCCONL(OSCCON | _OSCCON_OSWEN_MASK); //Start clock witching 0x872: MOV OSCCON, W2 0x874: MOV #0x57, W1 0x876: BSET W2, #0 0x878: MOV #0x46, W0 0x87A: MOV #0x742, W3 0x87C: MOV.B W0, [W3] 0x87E: MOV.B W1, [W3] 0x880: MOV.B W2, [W3] ! while (OSCCONbits.COSC != 0b001); //Wait for Clock switch to occur 0x882: MOV #0x7000, W2 0x884: MOV #0x1000, W1 0x886: MOV OSCCON, W3 0x888: AND W2, W3, W0 0x88A: SUB W0, W1, [W15] 0x88C: BRA NZ, .L2 ! while(OSCCONbits.LOCK!=1) {}; // Wait for PLL to lock 0x88E: MOV #0x20, W1 0x890: MOV OSCCON, W2 0x892: AND W1, W2, W0 0x894: BRA Z, .L4 ! //Fosc = 7.37/3*65/2 = 79.84MHz ! //Fcy = Fosc/2 = 39.9MHz !} 0x896: RETURN