Ага, есть решение!!! Большое спасибо, ты подсказал кардинальное
упрощение! -- DQM0 16,28,59,71 Input Pin DQMx control thel ower and upper bytes of the DQ buffers.
-- In read mode,
DQM3 the output buffers are place in a High-Z state.
-- During a WRITE cycle the input data is masked.
-- When DQMx is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses.
-- DQ0 through DQ7 are controlled by DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through DQ23 are controlled by DQM2. DQ24 through DQ31 are controlled by DQM3.