Схемы, платы, компоненты

bestsave on $\best.w
status_file $\progress.sts

unit mil
grid wire 1.000000 
grid via  1.000000 

rule pcb (pin_width_taper down (max_length 300))
rule pcb (width 5)  (clearance 5)
rule pcb (limit_vias 8)
rule pcb (clearance 7 (type smd_via))
rule pcb (clearance 7 (type pin_via))
rule pcb (via_at_smd off)

define (pair (nets BFS?+ BFS?- (gap 7)))
define (pair (nets BCLK?+ BCLK?- (gap 7)))
define (pair (nets BDX?+ BDX?- (gap 7)))
define (pair (nets BDR?+ BDR?- (gap 7)))
define (pair (nets TMS_DP TMS_DM (gap 7)))
define (pair (nets TTX+ TTX- (gap 7)))
define (pair (nets TRX+ TRX- (gap 7)))
define (pair (nets TX+ TX- (gap 7)))
define (pair (nets RX+ RX- (gap 7)))
define (pair (nets CYDP CYDM (gap 7.5)))
define (pair (nets DDCLK ~DDCLK (gap 7.5)))

set average_pair_length on

rule class PWR (width 10.0) (clearance 6 (type wire_wire)) 
rule class PLLPWR (width 9.0) (clearance 7 (type wire_wire)) 
rule class DIFFA (width 7.0) (clearance 10 (type wire_wire)) (limit_vias 2) (reorder daisy) (max_stub 0)
rule class DIFFB (width 7.0) (clearance 10 (type wire_wire)) (limit_vias 2) (reorder daisy) (max_stub 0)
rule class DIFF (width 7.0) (clearance 10 (type wire_wire) ) (limit_vias 2) (reorder daisy) (max_stub 0)
rule class U20 (width 7.5) (clearance 10 (type wire_wire)) (limit_vias 0) (reorder daisy) (max_stub 0)
rule class CLK (width 9) (clearance 8 (type wire_wire)) (limit_vias 4)
rule class ANAL (width 10.0) (clearance 10 (type wire_wire))  
rule class DDR (width 7.0) (clearance 7 (type wire_wire))
rule class IDE (width 7.0) (clearance 7 (type wire_wire)) 

rule net TCKR (reorder daisy) (max_stub 100)
rule net TCK (reorder daisy) (max_stub 100)
rule net DDCLK (reorder daisy) (max_stub 0)
rule net ~DDCLK (reorder daisy) (max_stub 0)

define (group g_tckr (fromto XC2-9 DD1-G3) (fromto DD1-G3 R33-1))
define (group g_tck (fromto XC2-11 D1-85) (fromto D1-85 R33-2))

define (region bga 
  (rect signal 3710 3100 4740 2100)
  (rule (width 5) (clearance 5)))

define (region bga_clk 
  (rect signal 3710 3100 4740 2100)
  (region_class CLK) (rule (width 7) (clearance 5)))

define (region bga_pwr 
  (rect signal 3710 3100 4740 2100)
  (region_class PWR) (rule (width 9) (clearance 5)))

define (region bga_pllpwr 
  (rect signal 3710 3100 4740 2100)
  (region_class PLLPWR) (rule (width 9) (clearance 5)))

define (region bga_ddr 
  (rect signal 3710 3100 4740 2100)
  (region_class DDR) (rule (width 7) (clearance 5)))

circuit class PWR (use_via min_via)
circuit class CLK (use_via min_via) 
circuit class DIFFA (use_via min_via) (match_net_length on (tolerance 101))
circuit class DIFFB (use_via min_via) (match_net_length on (tolerance 101))
circuit class ANAL (use_via min_via)
circuit class DDR (use_via min_via)
circuit class DIFF (use_via min_via)
circuit class IDE (use_via min_via)
circuit class U20 (use_via min_via)
circuit class PLLPWR (use_via min_via)
circuit class OTHER (use_via min_via)

direction TOP diagonal
direction INT1 diagonal
direction INT2 diagonal
#direction INT3 diagonal
#direction INT4 diagonal
direction BOTTOM diagonal

cost side_exit free
cost off_center free
cost layer Top free (type length)
cost layer Top free (type way)
cost layer Int1 free (type way)
cost layer Int2 free (type way)
#cost layer Int3 free (type way)
#cost layer Int4 free (type way)
cost layer Int1 free (type length)
cost layer Int2 free (type length)
#cost layer Int3 free (type length)
#cost layer Int4 free (type length)
cost layer Bottom free (type length)
cost layer Bottom free (type way)

protect all vias
protect all wires

via_at_smd off

select component DD1
fanout 1 (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)
unselect all objects

select net GND
select net V2V5 
select net V3V3
select all nets
protect selected nets
unselect all objects

bus diagonal
set diagonal_mode always

cost via medium
route 100
clean 2
tax way 4
tax via 4
route 60 70
clean 2
filter 1
route 60
clean 4
filter 1
route 150
clean 4
filter 1
route 150
clean 8


write wire $\host2a.w
center
spread  (extra 20 1)
miter (pin) (tjunction) (bend) (style diagonal)
critic
write wire $\host2a.m

write session $\host2a.ses
report status $\host2a.sts