Схемы, платы, компоненты

Low power capacitor-free two transistor DRAM architecture from imec can be stacked in 3D memories as part of a silicon back end of line (BEOL) process
Imec has developed a dynamic random-access memory (DRAM) cell architecture that eliminates the capacitor and so can be stacked in a 3D structure.
Classic DRAM designs beyond 32GByte struggle to scale as they get smaller, largely as a result of the capacitor. Instead, imec has shown a design with two low power indium-gallium-zinc-oxide thin-film transistors (IGZO-TFTs) and no storage capacitor. IGZO-TFTs are well known for very low off-current, and the parasitic capacitance of the read transistor serves as the storage element.

The 2T0C (2 transistor 0 capacitor) cell has a retention time longer than 400s, which further reduces the power consumption with a much longer refresh rate. This can be implemented on the back end of a CMOS process (BEOL) to put layers of dynamic memory on top of logic.

https://www.eenewseurope.com/news/imec-shows-capacitor-free-dram?fnid=134296