ARM, RISC-V контроллеры

Ничего не понимаю, добавил этот старап: STR71xSoftwareLibrary_Startup.s, там все обьявлено и и врубил таймер, что не так? //EIC->SIR[0] |= 0x000002; /* Configure the channel 0 priority */ EIC_SIR0 |= 0x000002; //EIC->IER |= 1<<0; /* Enable interrupts on channel 0 */ //EIC_IER0 |= 1; EIC_IER0 |= 31; //EIC->ICR |= 0x00000003; /* Enable interrupts irq and fiq*/ EIC_ICR |= 0x00000003; //TIM_Init(TIM0); TIM0_CR2 &= ~0x2000; TIM0_CR2 = 0x200F; TIM0_CR1 = 0x8000; TIM0_CNTR = 0x1; /***************************************************************************** * Copyright (c) 2007 Rowley Associates Limited. * * * * This file may be distributed under the terms of the License Agreement * * provided with this software. * * * * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * *****************************************************************************/ /***************************************************************************** * Preprocessor Definitions * ------------------------ * * STARTUP_FROM_RESET * * If defined, the program will startup from power-on/reset. If not defined * the program will just loop endlessly from power-on/reset. * * This definition is not defined by default on this target because the * debugger is unable to reset this target and maintain control of it over the * JTAG interface. The advantage of doing this is that it allows the debugger * to reset the CPU and run programs from a known reset CPU state on each run. * It also acts as a safety net if you accidently download a program in FLASH * that crashes and prevents the debugger from taking control over JTAG * rendering the target unusable over JTAG. The obvious disadvantage of doing * this is that your application will not startup without the debugger. * * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst * you are developing and only define STARTUP_FROM_RESET when development is * complete. * *****************************************************************************/ #define EMI_BASE 0x6C000000 #define EMI_BCON0_OFFSET 0x00 #define EMI_BCON1_OFFSET 0x04 #define EMI_BCON2_OFFSET 0x08 #define EMI_BCON3_OFFSET 0x0C #define PRCCU_BASE 0xA0000000 #define PRCCU_CFR_OFFSET 0x08 #define PRCCU_PLL1CR_OFFSET 0x18 #define PRCCU_MDIVR_OFFSET 0x40 #define PRCCU_PDIVR_OFFSET 0x44 #define PRCCU_BOOTCR_OFFSET 0x50 .section .vectors, "ax" .code 32 .align 0 .global reset_handler .global T0TIMI_Addr /***************************************************************************** * Exception Vectors * *****************************************************************************/ _vectors: #ifdef STARTUP_FROM_RESET ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ #else b . /* reset - infinite loop */ #endif ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ nop ldr pc, [pc, #irq_handler_address - . - 8] /* irq */ ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */ reset_handler_address: .word reset_handler undef_handler_address: .word undef_handler swi_handler_address: .word swi_handler pabort_handler_address: .word pabort_handler dabort_handler_address: .word dabort_handler irq_handler_address: .word irq_handler fiq_handler_address: .word fiq_handler #define EIC_base_addr 0xFFFFF800 /* EIC base address */ #define CICR_off_addr 0x04 /* Current Interrupt Channel Register.*/ #define ICR_off_addr 0x00 /* Interrupt Control register offset */ #define CIPR_off_addr 0x08 /* Current Interrupt Priority Register offset */ #define IVR_off_addr 0x18 /* Interrupt Vector Register offset */ #define FIR_off_addr 0x1C /* Fast Interrupt Register offset */ #define IER_off_addr 0x20 /* Interrupt Enable Register offset */ #define IPR_off_addr 0x40 /* Interrupt Pending Bit Register offset */ #define SIR0_off_addr 0x60 /* Source Interrupt Register 0 */ #define EMI_base_addr 0x6C000000 /* EMI base address */ #define BCON0_off_addr 0x00 /* Bank 0 configuration register offset */ #define BCON1_off_addr 0x04 /* Bank 1 configuration register offset */ #define BCON2_off_addr 0x08 /* Bank 2 configuration register offset */ #define BCON3_off_addr 0x0C /* Bank 3 configuration register offset */ #define EMI_ENABLE 0x8000 #define EMI_SIZE_16 0x0001 #define GPIO2_base_addr 0xE0005000 /* GPIO2 base address */ #define PC0_off_addr 0x00 /* Port Configuration Register 0 offset */ #define PC1_off_addr 0x04 /* Port Configuration Register 1 offset */ #define PC2_off_addr 0x08 /* Port Configuration Register 2 offset */ #define PD_off_addr 0x0C /* Port Data Register offset */ #define CPM_base_addr 0xA0000040 /* CPM Base Address */ #define BOOTCR_off_addr 0x10 /* CPM - Boot Configuration Register */ #define FLASH_mask 0x0000 /* to remap FLASH at 0x0 */ #define RAM_mask 0x0002 /* to remap RAM at 0x0 */ #define EXTMEM_mask 0x0003 /* to remap EXTMEM at 0x0 */ /*|----------------------------------------------------------------------------------| | - APB Bridge (System Peripheral) | |----------------------------------------------------------------------------------| */ #define APB1_base_addr 0xC0000000 /* APB Bridge1 Base Address */ #define APB2_base_addr 0xE0000000 /* APB Bridge2 Base Address */ #define CKDIS_off_addr 0x10 /* APB Bridge1 - Clock Disable Register */ #define SWRES_off_addr 0x14 /* APB Bridge1 - Software Reset Register */ #define CKDIS1_config_all 0x27FB /* To enable/disable clock of all APB1's peripherals */ #define SWRES1_config_all 0x27FB /* To reset all APB1's peripherals */ #define CKDIS2_config_all 0x7FDD /* To enable/disable clock of all APB2's peripherals */ #define SWRES2_config_all 0x7FDD /* To reset all APB2's peripherals */ .section .init, "ax" .code 32 .align 0 #ifndef PROCESSOR_CLOCK_FREQUENCY #define PROCESSOR_CLOCK_FREQUENCY 48000000 #endif /****************************************************************************** * * * Default exception handlers * * * ******************************************************************************/ reset_handler: #ifdef __FLASH_BUILD /* Copy exception vectors into RAM */ mov r8, #0x20000000 ldr r9, =_vectors ldmia r9!, {r0-r7} stmia r8!, {r0-r7} ldmia r9!, {r0-r6} stmia r8!, {r0-r6} #endif /* Map internal RAM to 0x00000000 */ ldr r0, =PRCCU_BASE ldr r1, [r0, #PRCCU_BOOTCR_OFFSET] bic r1, r1, #0x01 orr r1, r1, #0x02 str r1, [r0, #PRCCU_BOOTCR_OFFSET] // Note that PLL works from CLK2 which is CLK div 2 by default #if OSCILLATOR_CLOCK_FREQUENCY==16000000 #if PROCESSOR_CLOCK_FREQUENCY==32000000 ldr r1, =0x73 // set the PLL to x16 and div 4 == 32Mhz #elif PROCESSOR_CLOCK_FREQUENCY==48000000 ldr r1, =0x51 // set the PLL to x12 and div 2 == 48Mhz #endif #elif OSCILLATOR_CLOCK_FREQUENCY==4000000 #if PROCESSOR_CLOCK_FREQUENCY==32000000 ldr r1, =0x30 // set the PLL to x16 and div 1 == 32Mhz #elif PROCESSOR_CLOCK_FREQUENCY==48000000 ldr r1, =0x20 // set the PLL to x24 and div 1 == 48Mhz #endif #else #error OSCILLATOR_CLOCK_FREQUENCY not defined #endif str r1, [r0, #PRCCU_PLL1CR_OFFSET] ldr r1, =0x8008 /* Enable PLL */ str r1, [r0, #PRCCU_CFR_OFFSET] 1: ldr r1, [r0, #PRCCU_CFR_OFFSET] tst r1, #0x0002 beq 1b /* Wait for PLL to lock */ orr r1, r1, #1 /* Select PLL as system clock */ str r1, [r0, #PRCCU_CFR_OFFSET] ldr r1, =0x0000 /* CPU clock divider = 1 */ str r1, [r0, #PRCCU_MDIVR_OFFSET] ldr r1, =0x0000 /* APB clock dividers = 1 */ str r1, [r0, #PRCCU_PDIVR_OFFSET] /* Configure the EMI */ ldr r0, =EMI_BASE ldr r1, =0x801D str r1, [r0, #EMI_BCON1_OFFSET] /* Initialise peripherals */ LDR r1, =APB1_base_addr // r0= APB1 base address LDR r2, =APB2_base_addr // r0= APB2 base address LDR r0, =CKDIS1_config_all STRH r0, [r1, #CKDIS_off_addr] // Clock Disabling for all APB1 peripherals LDR r0, =CKDIS2_config_all STRH r0, [r2, #CKDIS_off_addr] // Clock Disabling for all APB2 peripherals LDR r0, =SWRES1_config_all STRH r0, [r1, #SWRES_off_addr] // Keep all APB1 peripherals under reset LDR r0, =SWRES2_config_all STRH r0, [r2, #SWRES_off_addr] // Keep all APB2 peripherals under reset MOV r7, #10 // Wait that the selected macrocells exit from reset loop1: SUBS r7, r7, #1 BNE loop1 MOV r0, #0 STRH r0, [r1, #SWRES_off_addr] // Enable all all APB1 peripherals STRH r0, [r2, #SWRES_off_addr] // Enable all all APB2 peripherals STRH r0, [r1, #CKDIS_off_addr] // Clock Enabling for all APB1 peripherals STRH r0, [r2, #CKDIS_off_addr] // Clock Enabling for all APB2 peripherals MOV r7, #10 // Wait that the selected macrocells exit from reset loop2: SUBS r7, r7, #1 BNE loop2 #ifdef ORIGINAL_INTERRUPT_SCHEME /* Initialise AIC */ LDR r3, =EIC_base_addr LDR r4, =0xE59F0000 STR r4, [r3, #IVR_off_addr] // Write the LDR pc,[pc,#offset] // instruction code in IVR[31:16] LDR r2, =32 // 32 Channel to initialize LDR r0, =T0TIMI_Addr // Read the address of the IRQs // address table LDR r1, =0x00000FFF AND r0,r0,r1 LDR r5, =SIR0_off_addr // Read SIR0 address SUB r4,r0,#8 // subtract 8 for prefetch LDR r1, =0xF7E8 // add the offset to the 0x00000000 // address(IVR address + 7E8 = 0x00000000) // 0xF7E8 used to complete the // LDR pc,[pc,#offset] opcode ADD r1,r4,r1 // compute the jump offset EIC_INI: MOV r4, r1, LSL #16 // Left shift the result STR r4, [r3, r5] // Store the result in SIRx register ADD r1, r1, #4 // Next IRQ address ADD r5, r5, #4 // Next SIR SUBS r2, r2, #1 // Decrement the number of SIR registers // to initialize BNE EIC_INI // If more then continue #else /* Program the AIC so that the IVR register holds the address of the current * interrupt's IRQ table entry */ ldr r3, =EIC_base_addr ldr r0, =T0TIMI_Addr // Read the start address of IRQ table ldr r1, =0xFFFF0000 and r0, r0, r1 // Mask off 16 LSBs str r0, [r3, #IVR_off_addr] // Write the 16 MSBs of the IRQ table address into the IVR add r3, r3, #SIR0_off_addr // Point to SIR0 ldr r0, =T0TIMI_Addr // Read the start address of IRQ table mov r0, r0, lsl #16 ldr r2, =32 1: str r0, [r3], #4 // Store 16 LSBs of IRQ table entry address in SIRn add r0, r0, #0x00040000 // Increment table pointer subs r2, r2, #1 // Decrement loop count bne 1b #endif /* Enable IRQ interrupts */ bl libarm_enable_irq /* Jump to the default C runtime startup code. */ b _start /****************************************************************************** * * * Default exception handlers * * These are declared weak symbols so they can be redefined in user code. * * * ******************************************************************************/ undef_handler: b undef_handler swi_handler: b swi_handler pabort_handler: b pabort_handler dabort_handler: b dabort_handler fiq_handler: b fiq_handler .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler /******************************************************************************* Peripherals IRQ handlers address table *******************************************************************************/ T0TIMI_Addr: .word T0TIMIIRQHandler FLASH_Addr: .word FLASHIRQHandler RCCU_Addr: .word RCCUIRQHandler RTC_Addr: .word RTCIRQHandler WDG_Addr: .word WDGIRQHandler XTI_Addr: .word XTIIRQHandler USBHP_Addr: .word USBHPIRQHandler I2C0ITERR_Addr: .word I2C0ITERRIRQHandler I2C1ITERR_ADDR: .word I2C1ITERRIRQHandler UART0_Addr: .word UART0IRQHandler UART1_Addr: .word UART1IRQHandler UART2_ADDR: .word UART2IRQHandler UART3_ADDR: .word UART3IRQHandler BSPI0_ADDR: .word BSPI0IRQHandler BSPI1_Addr: .word BSPI1IRQHandler I2C0_Addr: .word I2C0IRQHandler I2C1_Addr: .word I2C1IRQHandler CAN_Addr: .word CANIRQHandler ADC12_Addr: .word ADC12IRQHandler T1TIMI_Addr: .word T1TIMIIRQHandler T2TIMI_Addr: .word T2TIMIIRQHandler T3TIMI_Addr: .word T3TIMIIRQHandler .word 0 /* reserved */ .word 0 /* reserved */ .word 0 /* reserved */ HDLC_Addr: .word HDLCIRQHandler USBLP_Addr: .word USBLPIRQHandler .word 0 /* reserved */ .word 0 /* reserved */ T0TOI_Addr: .word T0TOIIRQHandler T0OC1_Addr: .word T0OC1IRQHandler T0OC2_Addr: .word T0OC2IRQHandler /****************************************************************************** /* Macro Name : SaveContext /* Description : This macro used to save the context before entering /* an exception handler. /* Input : The range of registers to store. /* Output : none /******************************************************************************/ .macro SaveContext reg1=, reg2= STMFD sp!,{\reg1-\reg2,lr} // Save The workspace plus the current return // address lr_ mode into the stack. MRS r1,spsr // Save the spsr_mode into r1. STMFD sp!,{r1} // Save spsr. .endm /****************************************************************************** * Macro Name : RestoreContext * Description : This macro used to restore the context to return from * an exception handler and continue the program execution. * Input : The range of registers to restore. * Output : none ******************************************************************************/ .macro RestoreContext reg1=, reg2= LDMFD sp!,{r1} // Restore the saved spsr_mode into r1. MSR spsr_cxsf,r1 // Restore spsr_mode. LDMFD sp!,{\reg1-\reg2,pc}^ // Return to the instruction following... // ...the exception interrupt. .endm /****************************************************************************** * Macro Name : IRQ_to_SYS * Description : This macro used to switch form IRQ mode to SYS mode * Input : none. * Output : none ******************************************************************************/ .macro IRQ_to_SYS MSR cpsr_c,#0x1F /* Switch to SYS mode */ STMFD sp!,{lr} /* Save the link register */ .endm /****************************************************************************** * Macro Name : SYS_to_IRQ * Description : This macro used to switch from SYS mode to IRQ mode * then to return to IRQHnadler routine. * Input : none. * Output : none. ******************************************************************************/ .macro SYS_to_IRQ LDMFD sp!,{lr} /* Restore the link register. */ MSR cpsr_c,#0xD2 /* Switch to IRQ mode. */ MOV pc,lr /* Return to IRQHandler routine to clear the */ /* pending bit. */ .endm /****************************************************************************** * Function Name : irq_handler * Description : This function called when IRQ exception is entered. * Input : none * Output : none ******************************************************************************/ irq_handler: SUB lr,lr,#4 /* Update the link register */ SaveContext r0,r12 /* Save the workspace plus the current */ /* return address lr_ irq and spsr_irq. */ LDR lr, =ReturnAddress /* Read the return address. */ LDR r0, =EIC_base_addr #ifdef ORIGINAL_INTERRUPT_SCHEME LDR r1, =IVR_off_addr ADD pc,r0,r1 /* Branch to the IRQ handler. */ #else ldr r0, [r0, #IVR_off_addr] /* Get the ISR table entry address */ ldr pc, [r0] /* Jump to ISR */ #endif ReturnAddress: /* Clear pending bit in EIC (using the proper IPRx) */ LDR r0, =EIC_base_addr LDR r2, [r0, #CICR_off_addr] /* Get the IRQ channel number. */ MOV r3,#1 MOV r3,r3,LSL r2 STR r3,[r0, #IPR_off_addr] /* Clear the corresponding IPR bit. */ RestoreContext r0,r12 /* Restore the context and return to the... */ /* ...program execution. */ /****************************************************************************** * Function Name : T0TIMIIRQHandler * Description : This function used to switch to SYS mode before entering * the T0TIMI_IRQHandler function located in 71x_it.c. * Then to return to IRQ mode after the * T0TIMI_IRQHandler function termination. * Input : none. * Output : none. ******************************************************************************/ T0TIMIIRQHandler: IRQ_to_SYS BL T0TIMI_IRQHandler SYS_to_IRQ /****************************************************************************** * Function Name : FLASHIRQHandler * Description : This function used to switch