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-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY adder IS
PORT (op1, op2 : IN unsigned(7 DOWNTO 0);
result : OUT INTEGER);
END adder;
ARCHITECTURE maxpld OF adder IS
BEGIN
result <= conv_integer(op1 + op2);
END maxpld;
Victor® (15.12.2003 14:37, просмотров: 813)