AVR (28.02.2008 17:17, просмотров: 222) ответил Gamma SPb на а вот туд уже неверно =) ровно 5 тактов. Даже диаграмки в ref man есть для однотактовых и двухтактовых инструкций
Хы. Цытата из шыта: However, certain conditions can increase interrupt latency by one cycle, depending on when the interrupt occurs. If a fixed latency is critical to the application, you should avoid the following conditions:
• Executing a MOV.D instruction that uses PSV to access a value in program memory space
• Appending an instruction stall cycle to any two-cycle instruction
• Appending an instruction stall cycle to any one-cycle instruction that performs a PSV
access
• A bit test and skip instruction (BTSC, BTSS) that uses PSV to access a value in the program
memory space