ARM, RISC-V контроллеры

sct:

LR_IROM1 0x08010000 0x000F0000 { ; load region size_region

ER_IROM1 0x08010000 0x000F0000 { ; load address = execution address

*.o (RESET, +First)

*(InRoot$$Sections)

.ANY (+RO)

.ANY (+XO)

}

RW_IRAM1 0x20000000 0x00038000 { ; RW data

.ANY (+RW +ZI)

}

}