ARM, RISC-V контроллеры

Он там есть, но насколько я понял он там усеченный. CYCCNT там нет. стр.345 

https://imagecraft.com/pub/ARM/DDI0419C.pdf

32.8 DWT (Data Watchpoint)

The Cortex ® -M0+ DWT implementation provides two watchpoint register sets.

32.8.1 DWT functionality

The processor watchpoints implement both data address and PC based watchpoint

functionality, a PC sampling register, and support comparator address masking, as

described in the ARMv6-M ARM ® .

32.8.2 DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the ARMv6-M

optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a

debugger to periodically sample the PC without halting the processor. This provides coarse

grained profiling. See the ARMv6-M ARM ® for more information.

The Cortex ® -M0+ DWT_PCSR records both instructions that pass their condition codes and

those that fail.