ARM, RISC-V контроллеры

Есть в первоисточниках 

https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-instruction-set/memory-access-instructions/ldr-and-str--immediate-offset

When Rt is PC in a word load instruction:

bit[0] of the loaded value must be 1 for correct execution

a branch occurs to the address created by changing bit[0] of the loaded value to 0

if the instruction is conditional, it must be the last instruction in the IT block.

и тут

https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-instruction-set/about-the-instruction-descriptions/address-alignment

Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To trap accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register