ARM, RISC-V контроллеры

я не знаю чего там военного но рукожопы из ST до сих пор не могут сделать правильный I2C - оно кривое по сей день. чтоб не быть голословным - цитата из эрраты на stm32h750 пилагается -> 

2.12 I2C

2.12.1 10-bit master mode: new transfer cannot be launched if first part

of the address is not acknowledged by the slave

Description

An I2C-bus master generates STOP condition upon non-acknowledge of I2C address that it

sends. This applies to 7-bit addresses as well as to each byte of 10-bit addresses.

When the device set as I2C-bus master transmits a 10-bit address of which the first byte (5-

bit header + 2 MSBs of the address + direction bit) is not acknowledged, the device duly

generates a STOP condition but it then cannot start any new I2C-bus transfer. In this

spurious state, the NACKF flag of the I2C_ISR register and the START bit of the I2C_CR2

register are both set, while the START bit should normally be cleared.

Workaround

In 10-bit-address master mode, if both NACKF flag and START bit get simultaneously set,

proceed as follows:

1. Wait for the STOP condition detection (STOPF = 1 in I2C_ISR register).

2. Disable the I2C peripheral.

3. Wait for a minimum of three APB cycles.

4. Enable the I2C peripheral again.

2.12.2 Wrong behavior in Stop mode when wakeup from Stop

mode is disabled in I2C

Description

If the wakeup from Stop mode by I2C is disabled (WUPEN = 0), the correct use of the I2C

peripheral is to disable it (PE = 0) before entering Stop mode, and re-enable it when back in

Run mode.

Some reference manual revisions may omit this information.

Failure to respect the above while the MCU operating as slave or as master in multi-master

topology enters Stop mode during a transfer ongoing on the I2C-bus may lead to the

following:

1. BUSY flag is wrongly set when the MCU exits Stop mode. This prevents from initiating

a transfer in Master mode, as the START condition cannot be sent when BUSY is set.

2. If clock stretching is enabled (NOSTRETCH = 0), the SCL line is pulled low by I2C and

the transfer stalled as long as the MCU remains in Stop mode.

The occurrence of such condition depends on the timing configuration, peripheral clock

frequency, and I2C-bus frequency.

This is a description inaccuracy issue rather than a product limitation.

Workaround

No application workaround is required.

Description of device limitations STM32H750xB/753xI

28/45 ES0396 Rev 9

2.12.3 Wrong data sampling when data setup time (tSU;DAT ) is shorter than

one I2C kernel clock period

Description

The I2C-bus specification and user manual specify a minimum data setup time (tSU;DAT) as:

• 250 ns in Standard mode

• 100 ns in Fast mode

• 50 ns in Fast mode Plus

The MCU does not correctly sample the I2C-bus SDA line when tSU;DAT is smaller than one

I2C kernel clock (I2C-bus peripheral clock) period: the previous SDA value is sampled

instead of the current one. This can result in a wrong receipt of slave address, data byte, or

acknowledge bit.

Workaround

Increase the I2C kernel clock frequency to get I2C kernel clock period within the transmitter

minimum data setup time. Alternatively, increase transmitter’s minimum data setup time. If

the transmitter setup time minimum value corresponds to the minimum value provided in the

I2C-bus standard, the minimum I2CCLK frequencies are as follows:

• In Standard mode, if the transmitter minimum setup time is 250 ns, the I2CCLK

frequency must be at least 4 MHz.

• In Fast mode, if the transmitter minimum setup time is 100 ns, the I2CCLK frequency

must be at least 10 MHz.

• In Fast-mode Plus, if the transmitter minimum setup time is 50 ns, the I2CCLK

frequency must be at least 20 MHz.

2.12.4 Spurious bus error detection in Master mode

Description

In Master mode, a bus error can be detected spuriously, with the consequence of setting the

BERR flag of the I2C_SR register and generating bus error interrupt if such interrupt is

enabled. Detection of bus error has no effect on the I2C-bus transfer in Master mode and

any such transfer continues normally.

Workaround

If a bus error interrupt is generated in Master mode, the BERR flag must be cleared by

software. No other action is required and the ongoing transfer can be handled normally.

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STM32H750xB/753xI Description of device limitations

40

2.12.5 Last-received byte loss in Reload mode

Description

If in Master receiver mode or Slave receive mode with SBC = 1 the following conditions are

all met:

• I2 C-bus stretching is enabled (NOSTRETCH = 0)

• RELOAD bit of the I2C_CR2 register is set

• NBYTES bitfield of the I2C_CR2 register is set to N greater than 1

• byte N is received on the I 2 C-bus, raising the TCR flag

• N - 1 byte is not yet read out from the data register at the instant TCR is raised,

then the SCL line is pulled low (I2C-bus clock stretching) and the transfer of the byte N from

the shift register to the data register inhibited until the byte N-1 is read and NBYTES bitfield

reloaded with a new value, the latter of which also clears the TCR flag. As a consequence,

the software cannot get the byte N and use its content before setting the new value into the

NBYTES field.

For I2C instances with independent clock, the last-received data is definitively lost (never

transferred from the shift register to the data register) if the data N - 1 is read within four

APB clock cycles preceding the receipt of the last data bit of byte N and thus the TCR flag

raising. Refer to the product reference manual or datasheet for the I2C implementation

table.

Workaround

• In Master mode or in slave mode with SBC = 1, use the Reload mode with

NBYTES = 1.

• In Master receiver mode, if the number of bytes to transfer is greater than 255, do not

use the Reload mode. Instead, split the transfer into sections not exceeding 255 bytes

and separate them with repeated START conditions.

• Make sure, for example through the use of DMA, that the byte N - 1 is always read

before the TCR flag is raised. Specifically for I2C instances with independent clock,

make sure that it is always read earlier than four APB clock cycles before the receipt of

the last data bit of byte N and thus the TCR flag raising.

The last workaround in the list must be evaluated carefully for each application as the timing

depends on factors such as the bus speed, interrupt management, software processing

latencies, and DMA channel priority.

Description of device limitations STM32H750xB/753xI

30/45 ES0396 Rev 9

2.12.6 Spurious master transfer upon own slave address match

Description

When the device is configured to operate at the same time as master and slave (in a multi-

master I2C-bus application), a spurious master transfer may occur under the following

condition:

• Another master on the bus is in process of sending the slave address of the device (the

bus is busy).

• The device initiates a master transfer by writing the I2C_CR2 register with its START

bit set before the slave address match event (the ADDR flag set in the I2C_ISR

register) occurs.

• After the ADDR flag is set:

– the device does not write I2C_CR2 before clearing the ADDR flag, or

– the device writes I2C_CR2 earlier than three I2C kernel clock cycles before

clearing the ADDR flag

In these circumstances, even though the START bit is automatically cleared by the circuitry

handling the ADDR flag, the device spuriously proceeds to the master transfer as soon as

the bus becomes free. The transfer configuration depends on the content of the I2C_CR2

register when the master transfer starts. Moreover, if the I2C_CR2 is written less than three

kernel clocks before the ADDR flag is cleared, the I2C peripheral may fall into an

unpredictable state.

Workaround

Upon the address match event (ADDR flag set), apply the following sequence.

Normal mode (SBC = 0):

1. Set the ADDRCF bit.

2. Before Stop condition occurs on the bus, write I2C_CR2 with the START bit low.

Slave byte control mode (SBC = 1):

1. Write I2C_CR2 with the slave transfer configuration and the START bit low.

2. Wait for longer than three I2C kernel clock cycles.

3. Set the ADDRCF bit.

4. Before Stop condition occurs on the bus, write I2C_CR2 again with its current value.

The time for the software application to write the I2C_CR2 register before the Stop condition

is limited, as the clock stretching (if enabled), is aborted when clearing the ADDR flag.

Polling the BUSY flag before requesting the master transfer is not a reliable workaround as

the bus may become busy between the BUSY flag check and the write into the I2C_CR2

register with the START bit set.

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STM32H750xB/753xI Description of device limitations

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2.12.7 START bit is cleared upon setting ADDRCF, not upon address match

Description

Some reference manual revisions may state that the START bit of the I2C_CR2 register is

cleared upon slave address match event.

Instead, the START bit is cleared upon setting, by software, the ADDRCF bit of the I2C_ICR

register, which does not guarantee the abort of master transfer request when the device is

being addressed as slave. This product limitation and its workaround are the subject of a

separate erratum.

Workaround

No application workaround is required for this description inaccuracy issue.

2.13 USART

2.13.1 Underrun flag is set when the USART is used in SPI Slave

receive mode

Description

When the USART is used in SPI Slave receive mode, the underrun flag (UDR bit in

USART_ISR register) may be set even if the transmitter is disabled (TE bit set to 0 in

USAR_CR1 register).

Workaround

Three workarounds are possible

• Ignore the UDR flag when the transmitter is disabled.

• Clear the UDR flag every time it is set, even if the Transmitter is disabled.

• Write dummy data in the USART_TDR register to avoid setting the UDR flag.

2.13.2 DMA stream locked when transferring data to/from USART/UART

Description

When a USART/UART is issuing a DMA request to transfer data, if a concurrent transfer

occurs, the requested transfer may not be served and the DMA stream may stay locked.

Workaround

Use the alternative peripheral DMA channel protocol by setting bit 20 of the DMA_SxCR

register.

This bit is reserved in the documentation and must be used only on the stream that

manages data transfers for USART/UART peripherals.