ARM, RISC-V контроллеры

	//Initialize ADC1 module by peripheral reset bus signal
	RCC->APB1RSTR |= RCC_APB2RSTR_ADC1RST; //Activate ADC1 reset signal;
	RCC->APB2RSTR; //Dummy read for a pause
	RCC->APB1RSTR &= ~RCC_APB2RSTR_ADC1RST;
	RCC->APB2RSTR; //Dummy read for a pause

	//Configure ADC1 registers
	ADC1->CR1 = 0 * ADC_CR1_AWDEN //Analog watchdog disabled on regular channels
	| 0 * ADC_CR1_JAWDEN //Analog watchdog disabled on injected channels
	| 0 * ADC_CR1_DUALMOD_3 | 0 * ADC_CR1_DUALMOD_2 | 0 * ADC_CR1_DUALMOD_1
			| 0 * ADC_CR1_DUALMOD_0 //Independed mode
			| 0 * ADC_CR1_DISCNUM_2 | 0 * ADC_CR1_DISCNUM_1
			| 0 * ADC_CR1_DISCNUM_0 //Discontinuous mode channel number (not used)
			| 0 * ADC_CR1_JDISCEN //Discontinuous mode on injected channels disabled
			| 0 * ADC_CR1_DISCEN //Discontinuous mode on regular channels disabled
			| 1 * ADC_CR1_JAUTO //Automatic injected group conversion enabled
			| 0 * ADC_CR1_AWDSGL //Analog watchdog enabled on all channels (not used)
			| 1 * ADC_CR1_SCAN //Scan mode enabled
			| 1 * ADC_CR1_JEOCIE //JEOC interrupt enabled
			| 0 * ADC_CR1_AWDIE //Analog watchdog interrupt disabled
			| 0 * ADC_CR1_EOCIE //EOC interrupt disabled
			| 0 * ADC_CR1_AWDCH_4 | 0 * ADC_CR1_AWDCH_3 | 0 * ADC_CR1_AWDCH_2
			| 0 * ADC_CR1_AWDCH_1 | 0 * ADC_CR1_AWDCH_0; //Analog watchdog is disabled
	ADC1->CR2 = 1 * ADC_CR2_TSVREFE //Temperature sensor and V REFINT channel enabled
	| 0 * ADC_CR2_SWSTART //Don't trigger regular channel software conversion start
	| 0 * ADC_CR2_JSWSTART //Don't trigger injected channel software conversion start
	| 1 * ADC_CR2_EXTTRIG //Conversion on external event enabled
	| 1 * ADC_CR2_EXTSEL_2 | 0 * ADC_CR2_EXTSEL_1 | 0 * ADC_CR2_EXTSEL_0 //Timer 3 TRGO event selected
	| 0 * ADC_CR2_JEXTTRIG //Injected channels conversion on external event is disabled
	| 1 * ADC_CR2_JEXTSEL_2 | 1 * ADC_CR2_JEXTSEL_1 | 1 * ADC_CR2_JEXTSEL_0 //JSWSTART is injected trigger
	| 0 * ADC_CR2_ALIGN //Right Alignment
	| 1 * ADC_CR2_DMA //DMA mode enabled
	| 0 * ADC_CR2_RSTCAL //Do not reset the calibration
	| 0 * ADC_CR2_CAL //Do not calibrate
	| 0 * ADC_CR2_CONT //Single conversion mode
	| 0 * ADC_CR2_ADON; //Don't turn on the ADC yet

	ADC1->SMPR1 = 1 * ADC_SMPR1_SMP17_2 //239.5 cycles sample time for Vrefint
	| 1 * ADC_SMPR1_SMP17_1 //
	| 1 * ADC_SMPR1_SMP17_0 //
	| 1 * ADC_SMPR1_SMP16_2 //239.5 cycles sample time for Temperature
	| 1 * ADC_SMPR1_SMP16_1 //
	| 1 * ADC_SMPR1_SMP16_0 //
	| 0 * ADC_SMPR1_SMP15_2 //13.5 cycles sample time for Channel 15
	| 1 * ADC_SMPR1_SMP15_1 //
	| 0 * ADC_SMPR1_SMP15_0 //
	| 0 * ADC_SMPR1_SMP14_2 //13.5 cycles sample time for Channel 14
	| 1 * ADC_SMPR1_SMP14_1 //
	| 0 * ADC_SMPR1_SMP14_0 //
	| 0 * ADC_SMPR1_SMP13_2 //13.5 cycles sample time for Channel 13
	| 1 * ADC_SMPR1_SMP13_1 //
	| 0 * ADC_SMPR1_SMP13_0 //
	| 0 * ADC_SMPR1_SMP12_2 //13.5 cycles sample time for Channel 12
	| 1 * ADC_SMPR1_SMP12_1 //
	| 0 * ADC_SMPR1_SMP12_0 //
	| 0 * ADC_SMPR1_SMP11_2 //13.5 cycles sample time for Channel 11
	| 1 * ADC_SMPR1_SMP11_1 //
	| 0 * ADC_SMPR1_SMP11_0 //
	| 0 * ADC_SMPR1_SMP10_2 //13.5 cycles sample time for Channel 10
	| 1 * ADC_SMPR1_SMP10_1 //
	| 0 * ADC_SMPR1_SMP10_0; //
	ADC1->SMPR2 =
			0 * ADC_SMPR2_SMP9_2 | 1 * ADC_SMPR2_SMP9_1 | 0 * ADC_SMPR2_SMP9_0 //13.5 cycles sample time for Channel 9
			| 0 * ADC_SMPR2_SMP8_2 | 1 * ADC_SMPR2_SMP8_1 | 0 * ADC_SMPR2_SMP8_0 //13.5 cycles sample time for Channel 8
			| 0 * ADC_SMPR2_SMP7_2 | 1 * ADC_SMPR2_SMP7_1 | 0 * ADC_SMPR2_SMP7_0 //13.5 cycles sample time for Channel 7
			| 0 * ADC_SMPR2_SMP6_2 | 1 * ADC_SMPR2_SMP6_1 | 0 * ADC_SMPR2_SMP6_0 //13.5 cycles sample time for Channel 6
			| 0 * ADC_SMPR2_SMP5_2 | 1 * ADC_SMPR2_SMP5_1 | 0 * ADC_SMPR2_SMP5_0 //13.5 cycles sample time for Channel 5
			| 0 * ADC_SMPR2_SMP4_2 | 1 * ADC_SMPR2_SMP4_1 | 0 * ADC_SMPR2_SMP4_0 //13.5 cycles sample time for Channel 4
			| 0 * ADC_SMPR2_SMP3_2 | 1 * ADC_SMPR2_SMP3_1 | 0 * ADC_SMPR2_SMP3_0 //13.5 cycles sample time for Channel 3
			| 0 * ADC_SMPR2_SMP2_2 | 1 * ADC_SMPR2_SMP2_1 | 0 * ADC_SMPR2_SMP2_0 //13.5 cycles sample time for Channel 2
			| 0 * ADC_SMPR2_SMP1_2 | 1 * ADC_SMPR2_SMP1_1 | 0 * ADC_SMPR2_SMP1_0 //13.5 cycles sample time for Channel 1
			| 0 * ADC_SMPR2_SMP0_2 | 1 * ADC_SMPR2_SMP0_1 | 0 * ADC_SMPR2_SMP0_0; //13.5 cycles sample time for Channel 0
	ADC1->JOFR1 = 0; //Injected channel 1 offset is not used
	ADC1->JOFR2 = 0; //Injected channel 2 offset is not used
	ADC1->JOFR3 = 0; //Injected channel 3 offset is not used
	ADC1->JOFR4 = 0; //Injected channel 4 offset is not used
	ADC1->HTR = 0; //ADC watchdog high threshold is not used
	ADC1->LTR = 0; //ADC watchdog low threshold is not used
	ADC1->SQR1 = 1 * ADC_SQR1_L_3 | 1 * ADC_SQR1_L_2 | 1 * ADC_SQR1_L_1
			| 1 * ADC_SQR1_L_0 //Regular channel sequence length is 16 conversions
			| 0 * ADC_SQR1_SQ16_4 //16th conversion at Ch9
			| 1 * ADC_SQR1_SQ16_3 //
			| 0 * ADC_SQR1_SQ16_2 //
			| 0 * ADC_SQR1_SQ16_1 //
			| 1 * ADC_SQR1_SQ16_0 //
			| 0 * ADC_SQR1_SQ15_4 //15th conversion at Ch8
			| 1 * ADC_SQR1_SQ15_3 //
			| 0 * ADC_SQR1_SQ15_2 //
			| 0 * ADC_SQR1_SQ15_1 //
			| 0 * ADC_SQR1_SQ15_0 //
			| 0 * ADC_SQR1_SQ14_4 //14th conversion at Ch15
			| 1 * ADC_SQR1_SQ14_3 //
			| 1 * ADC_SQR1_SQ14_2 //
			| 1 * ADC_SQR1_SQ14_1 //
			| 1 * ADC_SQR1_SQ14_0 //
			| 0 * ADC_SQR1_SQ13_4 //13th conversion at Ch14
			| 1 * ADC_SQR1_SQ13_3 //
			| 1 * ADC_SQR1_SQ13_2 //
			| 1 * ADC_SQR1_SQ13_1 //
			| 0 * ADC_SQR1_SQ13_0; //
	ADC1->SQR2 = 0 * ADC_SQR2_SQ12_4 //12th conversion at Ch7
	| 0 * ADC_SQR2_SQ12_3 //
	| 1 * ADC_SQR2_SQ12_2 //
	| 1 * ADC_SQR2_SQ12_1 //
	| 1 * ADC_SQR2_SQ12_0 //
	| 0 * ADC_SQR2_SQ11_4 //11th conversion at Ch6
	| 0 * ADC_SQR2_SQ11_3 //
	| 1 * ADC_SQR2_SQ11_2 //
	| 1 * ADC_SQR2_SQ11_1 //
	| 0 * ADC_SQR2_SQ11_0 //
	| 0 * ADC_SQR2_SQ10_4 //10th conversion at Ch5
	| 0 * ADC_SQR2_SQ10_3 //
	| 1 * ADC_SQR2_SQ10_2 //
	| 0 * ADC_SQR2_SQ10_1 //
	| 1 * ADC_SQR2_SQ10_0 //
	| 0 * ADC_SQR2_SQ9_4 //9th conversion at Ch4
	| 0 * ADC_SQR2_SQ9_3 //
	| 1 * ADC_SQR2_SQ9_2 //
	| 0 * ADC_SQR2_SQ9_1 //
	| 0 * ADC_SQR2_SQ9_0 //
	| 0 * ADC_SQR2_SQ8_4 //8th conversion at Ch3
	| 0 * ADC_SQR2_SQ8_3 //
	| 0 * ADC_SQR2_SQ8_2 //
	| 1 * ADC_SQR2_SQ8_1 //
	| 1 * ADC_SQR2_SQ8_0 //
	| 0 * ADC_SQR2_SQ7_4 //7th conversion at Ch2
	| 0 * ADC_SQR2_SQ7_3 //
	| 0 * ADC_SQR2_SQ7_2 //
	| 1 * ADC_SQR2_SQ7_1 //
	| 0 * ADC_SQR2_SQ7_0; //
	ADC1->SQR3 = 0 * ADC_SQR3_SQ6_4 //6th conversion at Ch1
	| 0 * ADC_SQR3_SQ6_3 //
	| 0 * ADC_SQR3_SQ6_2 //
	| 0 * ADC_SQR3_SQ6_1 //
	| 1 * ADC_SQR3_SQ6_0 //
	| 0 * ADC_SQR3_SQ5_4 //5th conversion at Ch0
	| 0 * ADC_SQR3_SQ5_3 //
	| 0 * ADC_SQR3_SQ5_2 //
	| 0 * ADC_SQR3_SQ5_1 //
	| 0 * ADC_SQR3_SQ5_0 //
	| 0 * ADC_SQR3_SQ4_4 //4th conversion at Ch13
	| 1 * ADC_SQR3_SQ4_3 //
	| 1 * ADC_SQR3_SQ4_2 //
	| 0 * ADC_SQR3_SQ4_1 //
	| 1 * ADC_SQR3_SQ4_0 //
	| 0 * ADC_SQR3_SQ3_4 //3rd conversion at Ch12
	| 1 * ADC_SQR3_SQ3_3 //
	| 1 * ADC_SQR3_SQ3_2 //
	| 0 * ADC_SQR3_SQ3_1 //
	| 0 * ADC_SQR3_SQ3_0 //
	| 0 * ADC_SQR3_SQ2_4 //2nd conversion at Ch11
	| 1 * ADC_SQR3_SQ2_3 //
	| 0 * ADC_SQR3_SQ2_2 //
	| 1 * ADC_SQR3_SQ2_1 //
	| 1 * ADC_SQR3_SQ2_0 //
	| 0 * ADC_SQR3_SQ1_4 //1st conversion at Ch10
	| 1 * ADC_SQR3_SQ1_3 //
	| 0 * ADC_SQR3_SQ1_2 //
	| 1 * ADC_SQR3_SQ1_1 //
	| 0 * ADC_SQR3_SQ1_0; //
	ADC1->JSQR = 0 * ADC_JSQR_JL_1 //1 injected conversion
	| 0 * ADC_JSQR_JL_0 //
	| 1 * ADC_JSQR_JSQ4_4 //Temperature channel (16) will be injecting
	| 0 * ADC_JSQR_JSQ4_3 //
	| 0 * ADC_JSQR_JSQ4_2 //
	| 0 * ADC_JSQR_JSQ4_1 //
	| 0 * ADC_JSQR_JSQ4_0; //

	//Configure DMA controller
	RCC->AHBENR |= RCC_AHBENR_DMA1EN; //Turn on DMA1 module clock
	RCC->AHBENR; //Dummy read for a pause
	DMA1_Channel1->CCR = 0; //Disable DMA1 channel 1 for configuration
	DMA1_Channel1->CPAR = (uint32_t) &ADC1->DR; //Set source peripheral address
	DMA1_Channel1->CMAR = (uint32_t) &ADCDMAbuff; //Set destination RAM address
	DMA1_Channel1->CNDTR = ADCchNum - ADCjChNum; //Move 16 ADC readings per cycle
	DMA1_Channel1->CCR = 0 * DMA_CCR1_MEM2MEM //Memory to memory mode disabled
	| 1 * DMA_CCR1_PL_1 | 0 * DMA_CCR1_PL_0 //Set high DMA priority
	| 0 * DMA_CCR1_MSIZE_1 | 1 * DMA_CCR1_MSIZE_0 //16 bit memory size
	| 0 * DMA_CCR1_PSIZE_1 | 1 * DMA_CCR1_PSIZE_0 //16 bit peripheral size
	| 1 * DMA_CCR1_MINC //Memory increment mode enabled
	| 0 * DMA_CCR1_PINC //Peripheral increment mode disabled
	| 1 * DMA_CCR1_CIRC //Circular mode enabled
	| 0 * DMA_CCR1_DIR //Data transfer from peripheral to memory
	//To do: process transfer error by restarting ADC and DMA
			| 0 * DMA_CCR1_TEIE //Transfer error interrupt disabled
			| 0 * DMA_CCR1_HTIE //Half transfer interrupt disabled
			| 0 * DMA_CCR1_TCIE //Transfer complete interrupt disabled (ADC interrupt after injected conversion is used)
			| 0 * DMA_CCR1_EN; //Don't enable DMA channel yet

	ADC1->CR2 |= ADC_CR2_ADON; //Turn on ADC1
	DMA1_Channel1->CCR |= DMA_CCR1_EN;	//Enable DMA channel for ADC1
	ADC1->SR = 0; //Clear ADC1 status flags