Схемы, платы, компоненты

Usually, before sending a START bit, the SDA and SCL lines should be checked for high levels.
If they are not, bus is in error condition. Recovery is to generate manually 9 STOP bits because if it is a glitch and data is hold low by slave(s), one of these STOP bit will go through and reset slaves. This series of 9 STOP bits should not check for clock stretch. The STOP bit could be continued until both SDA and SCL are high level, which is mandatory for START to occur.
If this technique is not possible, how about trying to use an MCU GPIO pin to supply voltage to EEPROMs and keep the enable different and static? GPIO max current seems compatible.

https://community.st.com/t5/stm32-mcus-products/re-synchronisation-of-2-m24m02-dr-eeproms/td-p/468229

Вот ещё должна была бы быть некая ссылка, но связи нет и интернет архив её не сохранил.
https://community.arm.com/support-forums/f/keil-forum/18781/problem-when-implement-i2c-interface-between-at24c04-eeprom-with-8051