Программируемая логика и ЦОС

ISE 10: Pack:1107 - Unable to combine the following symbols into a single IOB ... Что я делаю не так? 

Running directed packing...Pack:1107 - Unable to combine the following symbols into a single IOB   component:   	BUF symbol "PLL_BACK_OBUF" (Output Signal = PLL_BACK)   	PAD symbol "PLL_BACK" (Pad Signal = PLL_BACK)   A generic IO component of type IOB was chosen because the IO contains symbols   and/or properties consistent with input, output, or bi-directional usage and   contains no other symbols or properties that require a more specific IO   component type.   Each of the following constraints specifies an illegal physical site for a   component of type IOB:   	Symbol "PLL_BACK" (LOC=G16 [Physical Site Type = CLK_N])   The component type is determined by the types of logic and the properties and   configuration of the logic it contains. Please double check that the types of   logic elements and all of their relevant properties and configuration options   are compatible with the physical site type of the constraint.   Please correct the constraints accordingly.Pack:1107 - Unable to combine the following symbols into a single IOB   component:   	BUF symbol "NMI_OBUF" (Output Signal = NMI)   	PAD symbol "NMI" (Pad Signal = NMI)   A generic IO component of type IOB was chosen because the IO contains symbols   and/or properties consistent with input, output, or bi-directional usage and   contains no other symbols or properties that require a more specific IO   component type.   Each of the following constraints specifies an illegal physical site for a   component of type IOB:   	Symbol "NMI" (LOC=F16 [Physical Site Type = CLK_P])   The component type is determined by the types of logic and the properties and   configuration of the logic it contains. Please double check that the types of   logic elements and all of their relevant properties and configuration options   are compatible with the physical site type of the constraint.   Please correct the constraints accordingly.

top.vhd

entity top is	 port(		........................		PLL_BACK : out std_logic;		NMI : out std_logic;		........................);component sys_control	port(		........................		NMI : out std_logic;		........................);component pll_cpu	port(		CLK_IN :   in std_ulogic;		FEEDBACK : in std_ulogic;		RESET :    in std_ulogic;		PIN_OUT : out std_ulogic;		LOCKED :  out std_ulogic);	end component;pll_cpu_insertion : pll_cpu port map 		(	CLK_IN => PLL_XC_L,			FEEDBACK => PLL_XC_H,			PIN_OUT => PLL_BACK,			RESET => '0',			LOCKED => PLL_LOCKED		);sys_control_insertion : sys_control	port map(		NMI => NMI,pll_cpu.vhdlibrary IEEE;use IEEE.std_logic_1164.all; Library UNISIM;use UNISIM.vcomponents.all;entity pll_cpu is  port(       CLK_IN : in std_logic;       FEEDBACK : in std_logic;       RESET : in std_logic;       LOCKED : out std_logic;       PIN_OUT : out std_logic  );end pll_cpu;architecture pll_cpu of pll_cpu iscomponent BUFG  port (       I : in std_logic;       O : out std_logic  );end component;component DCM  generic(       CLKDV_DIVIDE : REAL := 2.0;       CLKFX_DIVIDE : INTEGER := 1;       CLKFX_MULTIPLY : INTEGER := 4;       CLKIN_DIVIDE_BY_2 : BOOLEAN := FALSE;       CLKIN_PERIOD : REAL := 0.0;       CLKOUT_PHASE_SHIFT : STRING := "NONE";       CLK_FEEDBACK : STRING := "1X";       DESKEW_ADJUST : STRING := "SYSTEM_SYNCHRONOUS";       DFS_FREQUENCY_MODE : STRING := "LOW";       DLL_FREQUENCY_MODE : STRING := "LOW";       DSS_MODE : STRING := "NONE";       DUTY_CYCLE_CORRECTION : BOOLEAN := TRUE;       FACTORY_JF : BIT_VECTOR := X"C080";       PHASE_SHIFT : INTEGER := 0;       STARTUP_WAIT : BOOLEAN := FALSE  );  port (       CLKFB : in std_logic := '0';       CLKIN : in std_logic := '0';       DSSEN : in std_logic := '0';       PSCLK : in std_logic := '0';       PSEN : in std_logic := '0';       PSINCDEC : in std_logic := '0';       RST : in std_logic := '0';       CLK0 : out std_logic := '0';       CLK180 : out std_logic := '0';       CLK270 : out std_logic := '0';       CLK2X : out std_logic := '0';       CLK2X180 : out std_logic := '0';       CLK90 : out std_logic := '0';       CLKDV : out std_logic := '0';       CLKFX : out std_logic := '0';       CLKFX180 : out std_logic := '0';       LOCKED : out std_logic := '0';       PSDONE : out std_logic := '0';       STATUS : out STD_LOGIC_VECTOR(7 downto 0) := "00000000"  );end component;signal NET345 : std_logic; beginU1 : DCM    port map(               CLKFB=>     FEEDBACK,        CLKIN=>     NET345,        DSSEN=>     '0',        PSCLK=>     '0',        PSEN=>      '0',                 PSINCDEC=>  '0',           RST=>       RESET,                CLK0=>      PIN_OUT,        CLK90=>     OPEN,        CLK180=>    OPEN,                CLK270=>    OPEN,             CLK2x=>     OPEN,           CLK2x180=>  OPEN,           CLKDV=>     OPEN,        CLKFX=>     OPEN,             CLKFX180=>  OPEN,           STATUS=>    OPEN,         PSDONE=>    OPEN,        LOCKED=>    LOCKED  );U2 : BUFG  port map(       I => CLK_IN,       O => NET345  );end pll_cpu;