ARM, RISC-V контроллеры

//вывод по ДМА от Тим2 в порт Ц 16 32р слов из pattern[17]. Начинается замес от сработки прерывания по ПЦ[7]
void timer2setup(void)
{
#define module 0x18f;		//100uS

	RCC->APB1PCENR |= RCC_TIM2EN;
	TIM2->INTFR|=0x0;
	TIM2->CTLR1=(dnCount|autoReload|edgeAligned|requestGen);
	TIM2->ATRLR=module;
	TIM2->CNT=0;
	TIM2->DMAINTENR|=TIM_UIE|TIM_UDE;
}

void DMAcommunicationSetup(void)
{
	RCC->AHBPCENR|=RCC_DMA1EN;
	DMA1_Channel2->CFGR=DMAofTimer2upload;
	DMA1_Channel2->PADDR=(uint32_t)&(GPIOC->BSHR);
	DMA1_Channel2->MADDR=(uint32_t)&(pattern[0]);
	DMA1_Channel2->CNTR=17;			//16+stop
	NVIC_EnableIRQ(DMA1_Channel2_IRQn);
}

const GPIO_cfgLow portCmodes={.bits.config0=out50MpushPull,.bits.config1=out50MpushPull,.bits.config2=out50MpushPull,.bits.config3=out50MpushPull \
		,.bits.config4=out50MpushPull,.bits.config5=out50MfuncPushPull,.bits.config6=out50MfuncPushPull,.bits.config7=inFloatMode};
void portsSetup(void)
{
	RCC->APB2PCENR |= RCC_IOPCEN;
	GPIOC->CFGLR=portCmodes.data;
}


...



void DMA1_Channel2_IRQHandler(void)
{
	TIM2->CTLR1&=~TIM_CEN;
	TIM2->CNT=1;
	DMA1->INTFCR=0xf<<4;
	DMA1_Channel2->CFGR&=~DMA_CFGR1_EN;
	DMA1_Channel2->PADDR=(uint32_t)&(GPIOC->BSHR);
	DMA1_Channel2->MADDR=(uint32_t)&(pattern[0]);		//[0] load in initiated interrupt
	DMA1_Channel2->CNTR=17;					//16+stop
}

void EXTI7_0_IRQHandler(void)
{
	EXTI->INTFR=0xffff;
		GPIOC->BSHR=pattern[0];		//DMA
		TIM2->CTLR1 |= TIM_CEN;
		TIM2->CNT=0x0;
		DMA1_Channel2->CFGR|=DMA_CFGR1_EN;
}