=mse= (23.10.2004 12:02, просмотров: 1) ответил =AK= на А не подскажете где взять описание форматов файлов DSN & DO Specctra?Вот, SM как-то давал примерчик, на всякий случай... ;тут их два, в обчем-то, что такое первый - не помню, а вот второй - типа для БГА с 1мм шагом бгёвинок, 6 слойка
;---------------------------------------------------
bestsave on $\best.w
status_file $\progress.sts
unit mil
grid wire 1.000000
grid via 5.000000
rule pcb (pin_width_taper down (max_length 80))
rule pcb (width 7) (clearance 7)
rule pcb (limit_vias 6)
rule pcb (clearance 8 (type smd_via))
rule pcb (clearance 8 (type pin_via))
rule pcb (via_at_smd off)
#define (bundle HPI_D (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets HD0 HD1 HD2 HD3))
#define (bundle HPI_D (add_net HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15))
#define (bundle XED_L (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets XED0 XED1 XED2 XED3))
#define (bundle XED_L (add_net XED4 XED5 XED6 XED7 XED8 XED9 XED10 XED11))
#define (bundle XED_L (add_net XED12 XED13 XED14 XED15))
#define (bundle XED_H (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets XED16 XED17 XED18 XED19))
#define (bundle XED_H (add_net XED20 XED21 XED22 XED23 XED24 XED25 XED26 XED27))
#define (bundle XED_H (add_net XED28 XED29 XED30 XED31))
#define (bundle XEA (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets XEA2 XEA3 XEA4 XEA5))
#define (bundle XEA (add_net XEA6 XEA7 XEA8 XEA9 XEA10 XEA11 XEA12 XEA13 XEA14 XEA15 XEA16))
#define (bundle YED_L (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets YED0 YED1 YED2 YED3))
#define (bundle YED_L (add_net YED4 YED5 YED6 YED7 YED8 YED9 YED10 YED11))
#define (bundle YED_L (add_net YED12 YED13 YED14 YED15))
#define (bundle YED_H (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets YED16 YED17 YED18 YED19))
#define (bundle YED_H (add_net YED20 YED21 YED22 YED23 YED24 YED25 YED26 YED27))
#define (bundle YED_H (add_net YED28 YED29 YED30 YED31))
#define (bundle YEA (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets YEA2 YEA3 YEA4 YEA5))
#define (bundle YEA (add_net YEA6 YEA7 YEA8 YEA9 YEA10 YEA11 YEA12 YEA13 YEA14 YEA15 YEA16))
define (pair (nets BFS?+ BFS?- (gap 8)))
define (pair (nets BCLK?+ BCLK?- (gap 8)))
define (pair (nets BDX?+ BDX?- (gap 8)))
define (pair (nets BDR?+ BDR?- (gap 8)))
set average_pair_length on
rule class POWER (width 14.0) (clearance 9 (type wire_wire))
rule class CVDD (width 18.0) (clearance 10 (type wire_wire))
rule class DIFF0 (width 10.0) (clearance 10 ) (limit_vias 1)
rule class DIFF1 (width 10.0) (clearance 10 ) (limit_vias 1)
rule class CLOCKS (width 12) (clearance 10 (type wire_wire)) (limit_vias 4)
rule class PLL (width 10) (clearance 10 (type wire_wire)) (limit_vias 2)
circuit class POWER (use_via medium_via) (priority 150)
circuit class CVDD (use_via medium_via) (priority 150)
circuit class CLOCKS (use_via medium_via) (priority 150)
circuit class DIFF0 (use_via min_via) (priority 150) (match_net_length on (tolerance 101))
circuit class DIFF1 (use_via min_via) (priority 150) (match_net_length on (tolerance 101))
circuit class OTHER (use_via min_via)
circuit class PLL (use_via min_via) (priority 200)
direction TOP diagonal
direction INT1 orthogonal
direction INT2 orthogonal
direction BOTTOM diagonal
cost side_exit free
cost off_center free
cost layer Top free (type length)
cost layer Top free (type way)
cost layer Int1 free (type length)
cost layer Int1 forbidden (type way)
cost layer Int2 free (type length)
cost layer Int2 forbidden (type way)
cost layer Bottom free (type length)
cost layer Bottom free (type way)
protect all vias
protect all wires
via_at_smd off
select component U1
select component U2
select component U3
select component U4
select component U5
select component U6
select component U7
select component U8
select component U9
select component U10
fanout 1 (direction in_out) (max_len 350) (location anywhere) (pin_share on) (smd_share on) (via_share on) (share_len 305) (pin_type power)
unselect all objects
select component U3
select component U4
select component U5
select component U6
select component U7
fanout 1 (smart_via_grid one_wire_between) (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)
unselect all objects
select component U1
select component U2
fanout 1 (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)
unselect all objects
bus diagonal
set diagonal_mode always
set dynamic_pinswap on
#select all bundle
select all pair
cost via high
route 40
protect selected_wires
unselect all objects
tax way 4
#forget bundle XED_L XED_H XEA YED_L YED_H YEA
#set diagonal_mode on
cost via medium
route 3
cost via high
route 20
clean 2
tax way 8
tax via 4
route 25 10
clean 2
route 25 30
clean 4
route 1
route 30 65
clean 8
write wire $\packer_a.w
center
spread (extra 20 1)
miter (pin) (tjunction) (bend) (style diagonal)
critic
write wire $\packer_a.m
write session $\packer_a.ses
report status $\packer_a.sts
;------------------------------------------------------------
bga pitch 1mm, 6 layers
;----------------------
status_file $\progress.sts
unit mil
grid wire 1.000000
grid via 1.000000
rule pcb (pin_width_taper down (max_length 300))
rule pcb (width 5) (clearance 5)
rule pcb (limit_vias 8)
rule pcb (clearance 7 (type smd_via))
rule pcb (clearance 7 (type pin_via))
rule pcb (via_at_smd off)
define (pair (nets BFS?+ BFS?- (gap 7)))
define (pair (nets BCLK?+ BCLK?- (gap 7)))
define (pair (nets BDX?+ BDX?- (gap 7)))
define (pair (nets BDR?+ BDR?- (gap 7)))
define (pair (nets TMS_DP TMS_DM (gap 7)))
define (pair (nets TTX+ TTX- (gap 7)))
define (pair (nets TRX+ TRX- (gap 7)))
define (pair (nets TX+ TX- (gap 7)))
define (pair (nets RX+ RX- (gap 7)))
define (pair (nets CYDP CYDM (gap 7.5)))
define (pair (nets DDCLK ~DDCLK (gap 7.5)))
set average_pair_length on
rule class PWR (width 10.0) (clearance 6 (type wire_wire))
rule class PLLPWR (width 9.0) (clearance 7 (type wire_wire))
rule class DIFFA (width 7.0) (clearance 10 (type wire_wire)) (limit_vias 2) (reorder daisy) (max_stub 0)
rule class DIFFB (width 7.0) (clearance 10 (type wire_wire)) (limit_vias 2) (reorder daisy) (max_stub 0)
rule class DIFF (width 7.0) (clearance 10 (type wire_wire) ) (limit_vias 2) (reorder daisy) (max_stub 0)
rule class U20 (width 7.5) (clearance 10 (type wire_wire)) (limit_vias 0) (reorder daisy) (max_stub 0)
rule class CLK (width 9) (clearance 8 (type wire_wire)) (limit_vias 4)
rule class ANAL (width 10.0) (clearance 10 (type wire_wire))
rule class DDR (width 7.0) (clearance 7 (type wire_wire))
rule class IDE (width 7.0) (clearance 7 (type wire_wire))
rule net TCKR (reorder daisy) (max_stub 100)
rule net TCK (reorder daisy) (max_stub 100)
rule net DDCLK (reorder daisy) (max_stub 0)
rule net ~DDCLK (reorder daisy) (max_stub 0)
define (group g_tckr (fromto XC2-9 DD1-G3) (fromto DD1-G3 R33-1))
define (group g_tck (fromto XC2-11 D1-85) (fromto D1-85 R33-2))
define (region bga
(rect signal 3710 3100 4740 2100)
(rule (width 5) (clearance 5)))
define (region bga_clk
(rect signal 3710 3100 4740 2100)
(region_class CLK) (rule (width 7) (clearance 5)))
define (region bga_pwr
(rect signal 3710 3100 4740 2100)
(region_class PWR) (rule (width 9) (clearance 5)))
define (region bga_pllpwr
(rect signal 3710 3100 4740 2100)
(region_class PLLPWR) (rule (width 9) (clearance 5)))
define (region bga_ddr
(rect signal 3710 3100 4740 2100)
(region_class DDR) (rule (width 7) (clearance 5)))
circuit class PWR (use_via min_via)
circuit class CLK (use_via min_via)
circuit class DIFFA (use_via min_via) (match_net_length on (tolerance 101))
circuit class DIFFB (use_via min_via) (match_net_length on (tolerance 101))
circuit class ANAL (use_via min_via)
circuit class DDR (use_via min_via)
circuit class DIFF (use_via min_via)
circuit class IDE (use_via min_via)
circuit class U20 (use_via min_via)
circuit class PLLPWR (use_via min_via)
circuit class OTHER (use_via min_via)
direction TOP diagonal
direction INT1 diagonal
direction INT2 diagonal
#direction INT3 diagonal
#direction INT4 diagonal
direction BOTTOM diagonal
cost side_exit free
cost off_center free
cost layer Top free (type length)
cost layer Top free (type way)
cost layer Int1 free (type way)
cost layer Int2 free (type way)
#cost layer Int3 free (type way)
#cost layer Int4 free (type way)
cost layer Int1 free (type length)
cost layer Int2 free (type length)
#cost layer Int3 free (type length)
#cost layer Int4 free (type length)
cost layer Bottom free (type length)
cost layer Bottom free (type way)
protect all vias
protect all wires
via_at_smd off
select component DD1
fanout 1 (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)
unselect all objects
select net GND
select net V2V5
select net V3V3
select all nets
protect selected nets
unselect all objects
bus diagonal
set diagonal_mode always
cost via medium
route 100
clean 2
tax way 4
tax via 4
route 60 70
clean 2
filter 1
route 60
clean 4
filter 1
route 150
clean 4
filter 1
route 150
clean 8
write wire $\host2a.w
center
spread (extra 20 1)
miter (pin) (tjunction) (bend) (style diagonal)
critic
write wire $\host2a.m
write session $\host2a.ses
report status $\host2a.sts