Микроконтроллеры

Проблема в Quartus 4.1 не хочет компилиться следующий код VHDL Я начинающий в ПЛИС, поэтому сильно не бейте. :) Это типа SPI слейв. Про ошибки эти в хелпе я читал, но пока не пойму как это относится к этому коду? И как их исправить. При компиляции выдаёт следующие сообщения: Код после сообщений. Error: VHDL error at SPI_Port.vhd(44): can't infer register for signal behavior:BusCycleDecode:bus_cycle_state.data_byte_out because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:bus_cycle_state.data_byte_out because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:instruct.read_data_gsm because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_cnt[0] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:address_cnt[0] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:data_cnt[0] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[7] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[6] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[5] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[4] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[3] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[2] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[1] because signal does not hold its value outside clock edge Error: VHDL error at SPI_Port.vhd(31): can't infer register for signal behavior:BusCycleDecode:code_in[0] because signal does not hold its value outside clock edge Error: Can't elaborate user hierarchy SPI_Port:inst Error: Quartus II Analysis & Synthesis was unsuccessful. 15 errors, 5 warnings Error: Processing ended: Mon Nov 08 21:03:36 2004 Error: Elapsed time: 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 15 errors, 5 warnings library IEEE; use IEEE.std_logic_1164.all; entity SPI_Port is port(mosi,sck,nce,wr,clk,reset: in std_logic; miso,rd: out std_logic; do: out std_logic_vector(7 downto 0); di: in std_logic_vector(7 downto 0)); end SPI_Port; architecture behave of SPI_Port is signal address: std_logic_vector(7 downto 0); begin behavior: block type instruct_type is (NONE, WRITE_DATA, READ_DATA, READ_DATA_GSM); signal instruct: instruct_type; begin BusCycleDecode: process(sck,nce,reset,mosi) type bus_cycle_type is (STAND_BY, CODE_BYTE, ADDRESS_BYTE, DATA_BYTE_IN, DATA_BYTE_OUT); variable bus_cycle_state: bus_cycle_type; variable code_cnt: natural := 0; variable address_cnt: natural := 0; variable data_cnt: natural := 0; variable code_in: std_logic_vector(7 downto 0); variable address_in: std_logic_vector(7 downto 0); begin if rising_edge(nce) then bus_cycle_state := STAND_BY; else case bus_cycle_state is when STAND_BY => if falling_edge(nce) then instruct <= NONE; code_cnt := 0; address_cnt := 0; data_cnt := 0; bus_cycle_state := CODE_BYTE; end if; when CODE_BYTE => if rising_edge(sck) then code_in(code_cnt) := mosi; code_cnt := code_cnt + 1; if code_cnt = 8 then case code_in is when "00100000" => instruct <= WRITE_DATA; bus_cycle_state := ADDRESS_BYTE; when "11000000" => instruct <= READ_DATA; bus_cycle_state := ADDRESS_BYTE; when "10100000" => instruct <= READ_DATA_GSM; bus_cycle_state := DATA_BYTE_OUT; when others => null; end case; end if; end if; when ADDRESS_BYTE => if rising_edge(sck) then address_in(address_cnt) := mosi; address_cnt := address_cnt + 1; if address_cnt = 8 then address <= address_in; if instruct = WRITE_DATA then bus_cycle_state := DATA_BYTE_IN; else bus_cycle_state := DATA_BYTE_OUT; end if; end if; end if; -- when DATA_BYTE_IN => -- if rising_edge(sck) then -- data_in(data_cnt) := mosi; -- data_cnt := data_cnt + 1; when others => code_cnt := 0; address_cnt := 0; data_cnt := 0; bus_cycle_state := CODE_BYTE; end case; end if; end process BusCycleDecode; end block behavior; end behave;