ARM, RISC-V контроллеры

SPI.1 Unintentional clearing of SPI interrupt flag
Introduction: The SPI interrupt flag is set by the SPI interface to generate an interrupt.  It is cleared by writing a 1 to this bit.
Problem: A write to any register associated with the SPI peripheral will clear the SPI interrupt register.
work-around: Avoid writing to SPI registers while transmissions are in progress or while SPI interrupts are pending.