ARM, RISC-V контроллеры

вот что сам производитель этой памяти говорит в аппнотах про разводку SDRAM: 

Related functionality makes minimizing skew critical, which requires signals of each group to be routed to similar electrical lengths. Routing address lines together on the same layer, and isolating data lanes from the address, command, and control groups will also help minimize skew. Match trace lengths for the data group within ±50 mil of each other to diminish skew; serpentine traces (back and forth traces in an “S” pattern to increase trace length) can be used to match lengths. In addition, some controllers require byte lanes to have matched trace lengths.

Вот другая рекомендация про разводку 64-МГц SDRAM:

• Avoid using vias in routing the trace of SDRAM clock signal. • The clock trace should be as short and wide as possible. • The resistances should be as close as possible to the SDCLK and SDCLKO pin. • Clock trace should have same layer and be as short as possible. • The SDCLKI trace length must be equal to the CLK trace length

Есть еще signal-integrity функции во многих пакетах.