Evgeny_CD, Архитектор (25.02.2010 00:46, просмотров: 136) ответил Evgeny_CD на Есть у них там какой-то ARM11MPCore -> Там говорится о "Snoop control unit for high performance and power efficient cache coherency"
О! Слова знакомые пошли :) ARM11 MPCore™ Processor Revision: r2p0 Technical Reference Manual ->. Level 1 Memory System. 7.1 Coherency protocol http://infocenter.arm.com/help/topic/com.arm.doc.ddi0360f/DDI0360F_arm11_mpcore_r2p0_trm.pdf
The coherency protocol is based on a MESI-type protocol. MESI is a write-invalidate cache protocol. When writing to a shared location, the related coherent cache line is invalidated in all other caches in the L1 memory system. Exclusive use is lost when another processor tries to read that shared location. Coherent cache line attributes can be:
Modified The cache line is present only in the current cache, and is dirty. It has been
modified from the value in main memory.
Exclusive The cache line is present only in the current cache, and is clean. It
matches main memory value.
Shared The cache line is present in more than one CPU cache and is clean. It
matches main memory value.
Invalid This coherent cache line is not present in the cache.