ARM, RISC-V контроллеры

Code fragment Stack_init LDR r2, =RAM_END ;Get top of RAM MRS r0, CPSR ;Save current processor mode ; Initialize the Undef mode stack BIC r1, r0, #0x1f ORR r1, r1, #0x1b MSR CPSR_c, r1 SUB sp,r2,#0x1F ;Keep top 32 bytes for flash programming routines. ; Initialize the Abort mode stack BIC r1, r0, #0x1f ORR r1, r1, #0x17 MSR CPSR_c, r1 SUB sp,r2,#0x5F ;Keep 64 bytes for Undef mode stack ; Initialize the IRQ mode stack BIC r1, r0, #0x1f ORR r1, r1, #0x12 MSR CPSR_c, r1 SUB sp,r2,#0x7F ;Keep 32 bytes for Abort mode stack ; Return to the original mode MSR CPSR_c, r0 ldr r3, =0x17F SUB sp,r2, r3 ; Initialize the stack for user application, ; keep 256 bytes for IRQ mode stack bl ARMInit VIC_init ldr r0, =VICDEFVECTADDR ldr r1, =NonVectIrq str r1, [r0] ldr r0, =VICVECTADDR0 ldr r1, =Tmr0Irq ; Save Tmr0Irq in vector address reg str r1, [r0] ldr r0, =VICVECTCNTL0 mov r1, #0x00000024 ; Ena Timer0 Irq str r1, [r0] ldr r0, =VICINTSELECT mov r1, #0x00000010 ; All interrupt are IRQ str r1, [r0] ldr r0, =VICINTENABLE mov r1, #0x00000010 ; Timer0 Enable str r1, [r0] Tmr0_init ldr r0, =T0TCR mov r1, #0x2 ; Conter reset, count is disable. str r1, [r0] ; Set reg. ldr r0, =T0PR mov r1, #0x00000200 ; Prescale=511, T0TC increment every 513 pclk. str r1, [r0] ; Set reg. ldr r0, =T0MR0 ldr r1, =0x00010000 ; Count up to 65536 ~1ms str r1, [r0] ; Set reg. ldr r0, =T0MCR mov r1, #0x0003 ; Interrupt when T0TC=T0MR0 str r1, [r0] ldr r0, =T0IR mov r1, #0x01 ; Reset interrupt str r1, [r0] ldr r0, =T0TCR mov r1, #0x1 ; Counter is enable. str r1, [r0] ; Set reg.