ARM, RISC-V контроллеры

i2c code ldr r0, =I2SCLL mov r1, #0xC8 ; 200 for low interval str r1, [r0] ldr r0, =I2SCLH mov r1, #0xC8 ; 200 for high interval str r1, [r0] ldr r0, =I2CONSET ; Load I2CONSET mov r1, #0x40 ; Set I2EN bit, I2C is enable strb r1, [r0] ; Store ldr r0, =I2DAT ldr r1, =I2STAT ldr r2, =I2CONSET ldr r3, =I2CONCLR ldr r4, [r2] ; Load I2CONSET orr r4, r4, #0x20 ; Set STA bit, transmition is running str r4, [r2] ; Store I2CWrite_0 ldrb r4, [r1] ; Load statue register. cmp r4, #0x08 bne I2CWrite_0 ; Status=0x08 if start condition has been tdransmited I2CWrite_0_a ldr r4, [r2] ; Load I2CONSET ands r4, r4, #0x08 ; Check SI bit beq I2CWrite_0_a ; Jump if SI=0, resume if SI=1 mov r4, #0xD0 strb r4, [r0] ; Store slave address at I2DAT ldr r4, [r3] ; Load I2CONCLR orr r4, r4, #0x08 ; Clear SI bit. strb r4, [r3] ldr r4, [r2] ; Load I2CONSET orr r4, r4, #0x40 ; Set I2EN bit str r4, [r2] ; Store I2CWrite_1 ldrb r4, [r1] ; Load statue register. cmp r4, #0x18 ; Status=0x18 if SLA+W has been transmitted, ACK has been received beq I2CWrite_1_a cmp r4, #0x20 ; Status=0x20 if SLA+W has been transmitted, not ACK has been received beq I2CWrite_1_a cmp r4, #0x38 ; Status=0x38 if Arbitration lost in SLA+W beq I2CWrite_1_a ; cmp r4, #0xf8 ; Status=0xf8, no relevant state information available ; beq I2CWrite_1_a b I2CWrite_1 I2CWrite_1_a bl LedSet ; For debuging purpose strb r9, [r2] ; Store sub address at i2cdat ldrb r4, [r3] orr r4, r4, #0x08 ; Clear SI bit. strb r4, [r3] I2CWrite_2 ldr r4, [r1] ; Load statue register. cmp r4, #0x28 bne I2CWrite_2 ; Status=0x28 if data byte has been transmitted, ACK has been received mov r5, #0x00 ; Clear Byte counter I2CWrite_start cmp r5, r11 beq I2CWrite_end ldrb r4, [r10], #0x01 ; Load a byte from LUT strb r4, [r0] ; Store byte at I2DAT ldrb r4, [r3] orr r4, r4, #0x08 ; Clear SI bit. strb r4, [r3] I2CWrite_3 ldr r4, [r1] ; Load statue register. cmp r4, #0x28 ; Check status bne I2CWrite_3 ; Status=0x28 if data byte has been transmitted, ACK has been received add r5, r5, #0x01 ; Byte Counter b I2CWrite_start I2CWrite_end ldr r4, [r2] ; Load I2CONSET orr r4, r4, #0x10 ; Set STO bit, transmition has ended str r4, [r2] ; Store