Микроконтроллеры AVR

Там страница перелистнулась, и URL стал другим. Копирую сюда Lord_Avon wrote:

I've managed to get my bit banged SPI working, and it was appallingly slow.

MBedder wrote:

"You just don't know how to cook'em!"(c) :))

.def tmp = r16 ; Scratchpad register, doesn't need to be saved/restored .equ sp_port = PORTB ; Port used for software SPI .equ csl_pin = PB0 ; Left channel CS line pin # .equ csr_pin = PB1 ; Right channel CS line pin # .equ sd_left = PB2 ; Left channel SD line pin # .equ sd_rght = PB3 ; Right channel SD line pin # .equ sck_pin = PB4 ; Common (L & R) SCK line pin # #define sclk sp_port,sck_pin ; Common (L & R) SCK line full alias ;------------------------------------------------------------------------------------------------------ ; Sends the X(L/H).N and Y(L/H).N bits to SD_LEFT and SD_RGHT resp. ; Usage example: SEND_XY H,7 - sends XH.7 to SD_LEFT and YH.7 to SD_RGHT ; The TMP bits corresponding to CSL, CSH and SCK must be cleared once prior to first SEND_XY invocation ; so they will appear as 0's at SP_PORT upon every SEND_XY execution ; .macro SEND_XY bld X@0,@1 ;; X(L/H).N -> T bit bst tmp,sd_left ;; T bit -> TMP.SD_LEFT bld Y@0,@1 ;; Y(L/H).N -> T bit bst tmp,sd_rght ;; T bit -> TMP.SD_RGHT out sp_port,tmp ;; SCLK = 0, CSL = 0, CSR = 0, SD_LEFT = X(L/H).N, SD_RGHT = Y(L/H).N sbi sclk ;; SCLK = 1. The slave devices latch the data on 0->1 SCLK transition .endm ;------------------------------------------------------------------------------------------------------ ;------------------------------------------------------------------------------------------------------ ; Simultaneous 2-channel 16-bit software SPI transmit only master. ; Input: X = channel 1 data (left), Y = channel 2 data (right). MSB.MSb transmits first ; Trashes: TMP ; 101 code words ; 120 CPU clocks ; Two 16-bit words are transmitted at ~ F_CPU/3.75 equivalent bit rate, ; which is only 1.7 times slower than a hardware SPI can deliver (~ F_CPU/2.2). ; Additionally, due to the simultaneous 2-channel transfers, this code doesn't introduce ; any interchannel delay which is unavoidable with a single channel hardware SPI. ; sspi16x2: in tmp,sp_port ; Read SP_PORT to TMP, clear CSL/CSR/SCK bits in TMP cbr tmp,(1 << csl_pin)|(1 << csr_pin)|(1 << sck_pin) ; SEND_XY H,7 ; Transmit XH.7 and YH.7 SEND_XY H,6 ; Transmit XH.6 and YH.6 SEND_XY H,5 ; Transmit XH.5 and YH.5 SEND_XY H,4 ; Transmit XH.4 and YH.4 SEND_XY H,3 ; Transmit XH.3 and YH.3 SEND_XY H,2 ; Transmit XH.2 and YH.2 SEND_XY H,1 ; Transmit XH.1 and YH.1 SEND_XY H,0 ; Transmit XH.0 and YH.0 SEND_XY L,7 ; Transmit XL.7 and YL.7 SEND_XY L,6 ; Transmit XL.6 and YL.6 SEND_XY L,5 ; Transmit XL.5 and YL.5 SEND_XY L,4 ; Transmit XL.4 and YL.4 SEND_XY L,3 ; Transmit XL.3 and YL.3 SEND_XY L,2 ; Transmit XL.2 and YL.2 SEND_XY L,1 ; Transmit XL.1 and YL.1 SEND_XY L,0 ; Transmit XL.0 and YL.0 sbr tmp,(1 << csl_pin)|(1 << csr_pin) ; Set TMP.CSL and TMP.CSR to 1 out sp_port,tmp ; Deselect the slaves ret ;------------------------------------------------------------------------------------------------------ Caution: don't even joke about porting it to C :))