Средства и методы разработки

Там же написано: Input Clock Frequency Changes and Clock Stop with CKE HIGH During CKE HIGH, LPDDR2 devices support input clock frequency changes and clock stop under the following conditions: • REFRESH requirements are met • Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands must have completed, including any associated data bursts, prior to changing the frequency • Related timing conditions, tRCD, tWR, tWRA, tRP, tMRW, and tMRR, etc., are met • CS# must be held HIGH • Only REFab or REFpb commands can be in process The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP. For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock cycle. After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL, etc. These settings may require adjustment to meet minimum timing requirements at the target clock frequency. For clock stop, CK is held LOW and CK# is held HIGH Т.е. меня в общем можно, но надо тщательно курить тему.