ARM, RISC-V контроллеры

Ответ: col 132 ;----------------------------------------------------------------------------- ; This file contains the startup code used by the ICCARM C compiler. ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; All code in the modules (except ?RESET) will be placed in the ICODE segment. ; ; $Revision: 1.7 $ ; ;----------------------------------------------------------------------------- ; ; Naming covention of labels in this file: ; ; ?xxx - External labels only accessed from assembler. ; __xxx - External labels accessed from or defined in C. ; xxx - Labels local to one module (note: this file contains ; several modules). ; main - The starting point of the user program. ; ;--------------------------------------------------------------- ; Macros and definitions for the whole file ;--------------------------------------------------------------- ; Mode, correspords to bits 0-5 in CPSR MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR USR_MODE DEFINE 0x10 ; User mode FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode IRQ_MODE DEFINE 0x12 ; Interrupt Request mode SVC_MODE DEFINE 0x13 ; Supervisor mode ABT_MODE DEFINE 0x17 ; Abort mode UND_MODE DEFINE 0x1B ; Undefined Instruction mode SYS_MODE DEFINE 0x1F ; System mode ;--------------------------------------------------------------- ; ?RESET ; Reset Vector. ; Normally, segment INTVEC is linked at address 0. ; For debugging purposes, INTVEC may be placed at other ; addresses. ; A debugger that honors the entry point will start the ; program in a normal way even if INTVEC is not at address 0. ;--------------------------------------------------------------- MODULE ?RESET RSEG CHECKSUM:CONST:NOROOT(2) COMMON INTVEC:CODE:NOROOT(2) PUBLIC __program_start EXTERN ?boot EXTERN undef_handler, swi_handler, prefetch_handler EXTERN data_handler, irq_handler, fiq_handler CODE32 ; Always ARM mode after reset org 0x00 __program_start ldr pc, [pc, #0x18] ; SoftReset ldr pc, [pc, #0x18] ; UndefHandler ldr pc, [pc, #0x18] ; SWIHandler ldr pc, [pc, #0x18] ; PrefetchAbortHandler ldr pc, [pc, #0x18] ; DataAbortHandler dc32 (SFE(CHECKSUM)-__program_start)/512+1 ldr pc, [pc,#-0xF20] ; IRQ : read the AIC ldr pc, [pc,#-0xF20] ; FIQ : read the AIC ;- There are only 5 offsets as the vectoring is used. PUBLIC SoftVectorVals SoftVectorVals: DCD SoftReset DCD UndefHandler DCD SWIHandler DCD PrefetchAbortHandler DCD DataAbortHandler ;- Vectoring Execution function run at absolut addresss SoftReset b ?boot UndefHandler b UndefHandler SWIHandler b SWIHandler PrefetchAbortHandler b PrefetchAbortHandler DataAbortHandler b DataAbortHandler org 0x20 LTORG ; ENDMOD __program_start ENDMOD ;--------------------------------------------------------------- ; ?BOOT ;--------------------------------------------------------------- PROGRAM ?BOOT RSEG ICODE:CODE:NOROOT(2) EXTERN ?cstartup EXTERN __program_start CODE32 PUBLIC ?boot ?boot: #include "AT91RM9200_inc.h" ldr r0,=AT91C_BASE_AIC ldr r1,=-1 str r1,[r0,#AIC_IDCR] ldr r0,=AT91C_MC_RCR //remap internal RAM @ 0 ldr r1,=1 str r1,[r0] #define START_FROM_ROM #ifdef START_FROM_ROM ldr r11,=0 ldr r12,=__program_start ldmia r12!,{r0-r10} //move vectors from ROM stmia r11!,{r0-r10} //to internal RAM @ 0 ldmia r12!,{r0-r6} stmia r11!,{r0-r6} #endif ;------------------------------------------------------------------------------ ;-Write in the MCKR dirty value concerning the clock selection CSS then overwrite it in a second sequence ;------------------------------------------------------------------------------ ;-Master Clock Register PMC_MCKR : "dirty CSS" is selected ldr r0, =(AT91C_PMC_CSS_PLLB_CLK | AT91C_PMC_PRES_CLK) str r0, [r1, #PMC_MCKR] //!!!!!Note: A new value to be written in PMC_MCKR //!!!!!must not be the same as the current value in PMC_MCKR. //!!!!! doc1768.pdf page 264 dummy_MCKR_Loop ldr r0, [r1, #PMC_SR] movs r0,r0,lsl #(31-3);AT91C_PMC_MCKRDY bpl dummy_MCKR_Loop #endif #ifndef SWITCH_TO_MAIN_CLK ;------------------------------------------------------------------------------ ;-Second sequence ;------------------------------------------------------------------------------ ;-Master Clock Register PMC_MCKR : Slow Clock is selected ldr r0, =(AT91C_PMC_CSS_SLOW_CLK | AT91C_PMC_PRES_CLK) str r0, [r1, #PMC_MCKR] ;- Reading the PMC Status register to detect when the Master Clock is commuted MCKR_Loop2 ldr r0, [r1, #PMC_SR] movs r0,r0,lsl #(31-3);AT91C_PMC_MCKRDY bpl MCKR_Loop2 #endif ;------------------------------------------------------------------------------ ;Step 0b. ;------------------------------------------------------------------------------ ;-After reset,PLLs are disabled ;-But in case of a boot already started, PLLs are turned off ;-Can be cleared if the project is used for a boot execution ;------------------------------------------------------------------------------ ldr r1, = AT91C_BASE_CKGR ; Get the CKGR Base Address ;-Master Clock Register PMC_PLLAR : Turned off PLLA ldr r0, = AT91C_CKGR_DIVA_0 str r0, [r1, #CKGR_PLLAR] ;-Master Clock Register PMC_PLLBR : Turned off PLLB ldr r0, = AT91C_CKGR_DIVB_0 str r0, [r1, #CKGR_PLLBR] /* ;------------------------------------------------------------------------------ ;Step 1. ;------------------------------------------------------------------------------ ;-Enabling the Main Oscillator ;-Normally First instruction in PMC initialisation ;------------------------------------------------------------------------------ ;-Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF ldr r0, = AT91C_CKGR_MOSCEN | AT91C_CKGR_OSCOUNT str r0, [r1, #CKGR_MOR] loop_for_rdy_main_osc1: ldr r0, [r1, #CKGR_MCFR] movs r0, r0, lsl #(31-16);(AT91C_CKGR_MAINRDY) bpl loop_for_rdy_main_osc1 #define SWITCH_TO_MAIN_CLK #ifdef SWITCH_TO_MAIN_CLK // switch to main clk multiplied by 4 ldr r1, = AT91C_BASE_PMC ; Get the PMC Base Address ldr r0, =(AT91C_PMC_CSS_MAIN_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_4) str r0, [r1, #PMC_MCKR] MCKR_Loop3 ldr r0, [r1, #PMC_SR] movs r0,r0,lsl #(31-3);AT91C_PMC_MCKRDY bpl MCKR_Loop3 #endif */ ; Execute C startup code. b ?cstartup ENDMOD ?boot ; Entry point = ?boot ;--------------------------------------------------------------- ; ?CSTARTUP ;--------------------------------------------------------------- MODULE ?CSTARTUP RSEG IRQ_STACK:DATA(2) RSEG SVC_STACK:DATA:NOROOT(2) RSEG CSTACK:DATA(2) RSEG ICODE:CODE:NOROOT(2) PUBLIC ?cstartup EXTERN ?main ; Execution starts here. ; After a reset, the mode is ARM, Supervisor, interrupts disabled. CODE32 ?cstartup ; Add initialization nedded before setup of stackpointers here ; Initialize the stack pointers. ; The pattern below can be used for any of the exception stacks: ; FIQ, IRQ, SVC, ABT, UND, SYS. ; The USR mode uses the same stack as SYS. ; The stack segments must be defined in the linker command file, ; and be declared above. mrs r0,cpsr ; Original PSR value bic r0,r0,#MODE_BITS ; Clear the mode bits orr r0,r0,#IRQ_MODE ; Set IRQ mode bits msr cpsr_c,r0 ; Change the mode ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK bic r0,r0,#MODE_BITS ; Clear the mode bits orr r0,r0,#SYS_MODE ; Set System mode bits msr cpsr_c,r0 ; Change the mode ldr sp,=SFE(CSTACK) & 0xFFFFFFF8 ; End of CSTACK ;---------------------------------------- ; Read/modify/write CP15 control register ;---------------------------------------- MRC p15, 0, r0, c1, c0,0 ; read cp15 control registre (cp15 r1) in r0 ldr r3, =0xC0000080 ; Reset bit :Little Endian end fast bus mode ldr r4, =0xC0000000 ; Set bit :Asynchronous clock mode, Not Fast Bus BIC r0, r0, r3 ORR r0, r0, r4 MCR p15, 0, r0, c1, c0,0 ; write r0 in cp15 control registre (cp15 r1) ;------------------------------------------------------------------------------ ;-Low level Init (PMC, AIC, EBI, ....) ;------------------------------------------------------------------------------ ;- Add loop to compensate Main Oscillator startup time ldr r0, =0x00000010 LoopOsc subs r0, r0, #1 bhi LoopOsc #ifdef __ARMVFP__ ; Enable the VFP coprocessor. mov r0, #0x40000000 ; Set EN bit in VFP fmxr fpexc, r0 ; FPEXC, clear others. ; Disable underflow exceptions by setting flush to zero mode. ; For full IEEE 754 underflow compliance this code should be removed ; and the appropriate exception handler installed. mov r0, #0x01000000 ; Set FZ bit in VFP fmxr fpscr, r0 ; FPSCR, clear others. #endif ; Add more initialization here ; Continue to ?main for more IAR specific system startup ldr r0,=?main bx r0 LTORG ENDMOD END