Микроконтроллеры

У меня есть опыт (и то не большой) с CAN контроллером ColdFire от Freescale вот выписка из документации, описывающая процесс инициализации

Initialization of the FlexCAN includes the initial configuration of the message buffers and configuration
of the CAN communication parameters following a reset, as well as any reconfiguration that may be
required during operation. The FlexCAN module may be reset in three ways:
• Device level hard reset—resets all memory mapped registers asynchronously
• Device level soft reset—resets some of the memory mapped registers synchronously (refer to
Table 32-1 to see which registers are affected by soft reset)
• CANMCR[SOFT_RST] bit—has the same effect as the device level soft reset
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The CANMCR[SOFT_RST] bit
remains asserted while soft reset is pending, so software can poll this bit to know when the reset has
completed. Also, soft reset can not be applied while clocks are shut down in any of the low power modes.
The low power mode should be exited and the clocks resumed before applying soft reset.
The clock source, CANCTRL[CLK_SRC], should be selected while the module is in disable mode. After
the clock source is selected and the module is enabled (CANMCR[MDIS] bit cleared), the FlexCAN
automatically enters freeze mode. In freeze mode, the FlexCAN is un-synchronized to the CAN bus, the
CANMCR register’s HALT and FRZ bits are set, the internal state machines are disabled, and the
CANMCR register’s FRZ_ACK and NOT_RDY bits are set. The CANTX pin is in recessive state and the
FlexCAN does not initiate any transmission or reception of CAN frames. The message buffers are not
affected by reset, so they are not automatically initialized.
For any configuration change/initialization, the FlexCAN must be in freeze mode (see Section 32.1.3.2,
“Freeze Mode”). The following is a generic initialization sequence applicable to the FlexCAN module:
1. Initialize all operation modes in the CANCTRL register.
a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW.
b) Select the S-clock rate by programming the PRESDIV field.
c) Select the internal arbitration mode via the LBUF bit.
2. Initialize message buffers.
a) The control/status word of all message buffers must be written as an active or inactive message
buffer
b) All other entries in each message buffer should be initialized as required
3. Initialize RXGMASK, RX14MASK, and RX15MASK registers for acceptance mask as needed.
4. Initialize FlexCAN interrupt handler.
a) Initialize the interrupt controller registers for any needed interrupts. See Chapter 16, “Interrupt
Controller Module,” for more information.
b) Set the required mask bits in the IMASK register (for all message buffer interrupts) and the
CANCTRL (for bus off and error interrupts).
5. Clear the CANMCR[HALT] bit. At this point, the FlexCAN attempts to synchronize with the CAN
bus.