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... inter-digit blanking time should be added between grid pulse timings as shown in Fig.9(b). Generally the inter-digit blanking time should be approximately 10 to 50usec, but this can vary depending on the delay time. Delay time occurs when high value pull down resistor type drivers are used or when the drive circuit is situated away from the VFD. We recommend that an appropriate inter-digit blanking time is utilized on the grid signal only, rather than on both grid and anode signals.