ARM, RISC-V контроллеры

Там что-то идёт в комплекте с Sourcery. Я подрихтовал под свои нужды: startup.c: #include "stm32f2regs.h" #include "cs3.h" #include <string.h> extern void __libc_init_array(void); extern int main(); union intvec_elem { void (*fptr)(void); void *dptr; }; static void trap(void) { for (;;) { /* it's a trap! */ } } static union intvec_elem vectab[] __attribute((used, section(".cs3.vectab"))) = { { .dptr = __cs3_stack }, { __cs3_start_c }, { trap }, /* NMI */ { trap }, /* HardFault */ { trap }, /* MemManage */ { trap }, /* BusFault */ { trap }, /* UsageFault */ { 0 }, { 0 }, { 0 }, { 0 }, { trap }, /* SVC */ { trap }, /* DebugMon */ { 0 }, { trap }, /* PendSV */ { trap }, /* SysTick */ }; static void mcu_init(void) { uint32_t tmp = 0x0703; FLASH_ACR = tmp; /* 3 wait states, acceleration enabled */ while (FLASH_ACR != tmp) { /* wait */ } RCC_PLLCFGR = 0x080030CD; /* M=13, N=195, P=2, Q=8 */ REGBIT(RCC_CR, 24) = 1; /* PLL on */ RCC_CFGR = 0x00009402; /* use PLL as clock source */ } void __attribute ((noreturn)) __cs3_start_c(void) { const struct __cs3_region* r = &__cs3_regions[0]; mcu_init(); /* Initialize memory */ memcpy(r->data, r->init, r->init_size); memset(r->data + r->init_size, 0, r->zero_size); /* Run initializers. */ __libc_init_array(); (void)main(); for (;;) {} } stm32.ld:

ENTRY(__cs3_start_c)
SEARCH_DIR(.)

MEMORY
{
  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 192k
  rom (rx) : ORIGIN = 0x08000000, LENGTH = 512k
  option_bytes_rom (rx) : ORIGIN = 0x1ffff800, LENGTH = 16
}

PROVIDE(__cs3_heap_start = _end);
PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

SECTIONS
{
  .text :
  {
    KEEP(*(.cs3.vectab))

    *(.text .text.* .gnu.linkonce.t.*)
    *(.plt)
    *(.gnu.warning)
    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

    *(.ARM.extab* .gnu.linkonce.armextab.*)
    *(.gcc_except_table)
  } >rom
  .eh_frame_hdr : ALIGN (4)
  {
    KEEP (*(.eh_frame_hdr))
    *(.eh_frame_entry .eh_frame_entry.*)
  } >rom
  .eh_frame : ALIGN (4)
  {
    KEEP (*(.eh_frame)) *(.eh_frame.*)
  } >rom
  /* .ARM.exidx is sorted, so has to go in its own output section.  */
  PROVIDE_HIDDEN (__exidx_start = .);
  .ARM.exidx :
  {
    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
  } >rom
  PROVIDE_HIDDEN (__exidx_end = .);
  .rodata : ALIGN (4)
  {
    *(.rodata .rodata.* .gnu.linkonce.r.*)

    . = ALIGN(4);
    KEEP(*(.init))

    . = ALIGN(4);
    __preinit_array_start = .;
    KEEP (*(.preinit_array))
    __preinit_array_end = .;

    . = ALIGN(4);
    __init_array_start = .;
    KEEP (*(SORT(.init_array.*)))
    KEEP (*(.init_array))
    __init_array_end = .;

    . = ALIGN(4);
    KEEP(*(.fini))

    . = ALIGN(4);
    __fini_array_start = .;
    KEEP (*(.fini_array))
    KEEP (*(SORT(.fini_array.*)))
    __fini_array_end = .;

    . = ALIGN(0x4);
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*crtend.o(.ctors))

    . = ALIGN(0x4);
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*crtend.o(.dtors))

    . = ALIGN(4);
    __cs3_regions = .;
    LONG (0)
    LONG (__cs3_region_init_ram)
    LONG (__cs3_region_start_ram)
    LONG (__cs3_region_init_size_ram)
    LONG (__cs3_region_zero_size_ram)
    __cs3_regions_end = .;
    . = ALIGN (8);
    *(.rom)
    *(.rom.b .bss.rom)
    _etext = .;
  } >rom
  __cs3_region_size_rom = LENGTH(rom);

  ASSERT (!(__cs3_region_init_ram & 7), "__cs3_region_init_ram not aligned")
  ASSERT (!(__cs3_region_start_ram & 7), "__cs3_region_start_ram not aligned")
  ASSERT (!(__cs3_region_init_size_ram & 7), "__cs3_region_init_size_ram not aligned")
  ASSERT (!(__cs3_region_zero_size_ram & 7), "__cs3_region_zero_size_ram not aligned")
  .cs3.option_bytes_rom : ALIGN (8)
  {
    __cs3_region_start_option_bytes_rom = .;
    *(.cs3.region-head.option_bytes_rom)
    *(.option_bytes_rom)
    . = ALIGN (8);
  } >option_bytes_rom
  .cs3.option_bytes_rom.bss :
  {
    *(.option_bytes_rom.b .bss.option_bytes_rom)
    . = ALIGN (8);
  } >option_bytes_rom
  __cs3_region_size_option_bytes_rom = LENGTH(option_bytes_rom);
  __cs3_region_init_option_bytes_rom = LOADADDR (.cs3.option_bytes_rom);
  __cs3_region_init_size_option_bytes_rom = LOADADDR (.cs3.option_bytes_rom.bss) - LOADADDR (.cs3.option_bytes_rom);
  __cs3_region_zero_size_option_bytes_rom = SIZEOF(.cs3.option_bytes_rom.bss);

  .data : ALIGN (8)
  {
    __cs3_region_start_ram = .;
    *(.cs3.region-head.ram)
    KEEP(*(.jcr))
    *(.got.plt) *(.got)
    *(.shdata)
    *(.data .data.* .gnu.linkonce.d.*)
    . = ALIGN (8);
    *(.ram)
    . = ALIGN (8);
    _edata = .;
  } >ram AT>rom
  .bss : ALIGN (8)
  {
    *(.shbss)
    *(.bss .bss.* .gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN (8);
    *(.ram.b .bss.ram)
    . = ALIGN (8);
    _end = .;
    __end = .;
  } >ram AT>rom
  __cs3_region_size_ram = LENGTH(ram);
  __cs3_region_init_ram = LOADADDR (.data);
  __cs3_region_init_size_ram = _edata - ADDR (.data);
  __cs3_region_zero_size_ram = _end - _edata;

  .stab 0 (NOLOAD) : { *(.stab) }
  .stabstr 0 (NOLOAD) : { *(.stabstr) }
  /* DWARF debug sections.
   * Symbols in the DWARF debugging sections are relative to
   * the beginning of the section so we begin them at 0.
   */
  /* DWARF 1 */
  .debug          0 : { *(.debug) }
  .line           0 : { *(.line) }
  /* GNU DWARF 1 extensions */
  .debug_srcinfo  0 : { *(.debug_srcinfo) }
  .debug_sfnames  0 : { *(.debug_sfnames) }
  /* DWARF 1.1 and DWARF 2 */
  .debug_aranges  0 : { *(.debug_aranges) }
  .debug_pubnames 0 : { *(.debug_pubnames) }
  /* DWARF 2 */
  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
  .debug_abbrev   0 : { *(.debug_abbrev) }
  .debug_line     0 : { *(.debug_line) }
  .debug_frame    0 : { *(.debug_frame) }
  .debug_str      0 : { *(.debug_str) }
  .debug_loc      0 : { *(.debug_loc) }
  .debug_macinfo  0 : { *(.debug_macinfo) }
  /* DWARF 2.1 */
  .debug_ranges   0 : { *(.debug_ranges) }
  /* SGI/MIPS DWARF 2 extensions */
  .debug_weaknames 0 : { *(.debug_weaknames) }
  .debug_funcnames 0 : { *(.debug_funcnames) }
  .debug_typenames 0 : { *(.debug_typenames) }
  .debug_varnames  0 : { *(.debug_varnames) }

  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
  /DISCARD/ : { *(.note.GNU-stack) }
}