ARM, RISC-V контроллеры

Работающий пример для IAR: /*************** In main.c : ***************/ #pragma vector=0x18 __irq __arm void irq_handler(void) { void (*interrupt_function)(); unsigned int vector; vector = VICVectAddr; // Get interrupt vector. interrupt_function = (void(*)())vector; (*interrupt_function)(); // Call vectored interrupt function. VICVectAddr = 0; // Clear interrupt in VIC.} void InitTimer0Interrupt(void(*timer_func)()) { timer_function = timer_func; VICIntSelect &= ~VIC_TIMER0_bit; VICVectAddr0 = (unsigned int)&Timer0Interrupt; VICVectCntl0 = 0x20 | VIC_TIMER0; VICIntEnable = VIC_TIMER0_bit; } static void Timer0Interrupt() { T0IR = 0xff; // Clear timer 0 interrupt line. } /********** cstartup.s79: *****************/ MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR USR_MODE DEFINE 0x10 ; User mode FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode IRQ_MODE DEFINE 0x12 ; Interrupt Request mode SVC_MODE DEFINE 0x13 ; Supervisor mode ABT_MODE DEFINE 0x17 ; Abort mode UND_MODE DEFINE 0x1B ; Undefined Instruction mode SYS_MODE DEFINE 0x1F ; System mode MODULE ?RESET COMMON INTVEC:CODE:NOROOT(2) PUBLIC __program_start EXTERN ?cstartup EXTERN irq_handler ; CODE32 ; Always ARM mode after reset org 0x00 __program_start ldr pc,=?cstartup ; Absolute jump can reach 4 GByte org 0x04 undef_handler ldr pc,=undef_handler org 0x08 swi_handler ldr pc,=swi_handler org 0x0c prefetch_handler ldr pc,=prefetch_handler org 0x10 data_handler ldr pc,=data_handler ; org 0x18 ;defined in main.c ; ldr pc,=irq_handler org 0x1c fiq_handler ldr pc,=fiq_handler org 0x20 LTORG ENDMOD MODULE ?CSTARTUP RSEG IRQ_STACK:DATA(2) RSEG SVC_STACK:DATA(2) RSEG CSTACK:DATA(2) RSEG ICODE:CODE:NOROOT(2) PUBLIC ?cstartup EXTERN ?main CODE32 ?cstartup mrs r0,cpsr ; Original PSR value bic r0,r0,#MODE_BITS ; Clear the mode bits orr r0,r0,#SVC_MODE ; Set IRQ mode bits msr cpsr_c,r0 ; Change the mode ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of SVC_STACK bic r0,r0,#MODE_BITS ; Clear the mode bits orr r0,r0,#IRQ_MODE ; Set IRQ mode bits msr cpsr_c,r0 ; Change the mode ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK bic r0,r0,#MODE_BITS ; Clear the mode bits orr r0,r0,#SYS_MODE ; Set System mode bits msr cpsr_c,r0 ; Change the mode ldr sp,=SFE(CSTACK) & 0xFFFFFFF8 ; End of CSTACK ldr r0,=?main bx r0 LTORG ENDMOD