ARM, RISC-V контроллеры

  
FLASH_SetLatency(FLASH_Latency_2);   //          
  /*
     
      FLASH_Latency_0: FLASH Zero Latency cycle 
      FLASH_Latency_1: FLASH One Latency cycle 
      FLASH_Latency_2: FLASH Two Latency cycles 
    
    Flash access control register ()
    
    Address offset: 0x00
    Reset value: 0x0000 0030
    
    Bits 31:6 Reserved, must be kept at reset value.
    
    Bit 5PRFTBS: Prefetch buffer status
    This bit provides the status of the prefetch buffer.
    0: Prefetch buffer is disabled
    1: Prefetch buffer is enabled
    
    Bit 4PRFTBE: Prefetch buffer enable
    0: Prefetch is disabled
    1: Prefetch is enabled
    
    Bit 3HLFCYA: Flash half cycle access enable
    0: Half cycle is disabled
    1: Half cycle is enabled
    
    Bits 2:0 LATENCY: Latency
    These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
    
    000 Zero wait state, if 0 < SYSCLK=24 MHz
    001 One wait state, if 24 MHz < SYSCLK =48 MHz
    010 Two wait states, if 48 MHz < SYSCLK =72 MHz
  */   
    FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_Disable);