Evgeny_CD (11.05.2006 21:05, просмотров: 1) ответил AlexandrY на Нуу... это не аргументы.
Кстати, а на живом STR91xxx еще ничего не запускали? А тот я тут ерату внимательно почитал - ST в своем духе... System reset at 96 MHz
Description of limitation in Rev B and Rev D
When the CPU is fetching instruction from the Flash memory at 96MHz FMI clock, the flash
memory must be configured to operate at 2 wait state.
When a system reset occurs, the CPU's clock control registers remain unchanged and the
FMI clock keeps operating at 96 MHz. However, the Flash Configuration Register is reset by
the system reset from 2 wait states to 1 wait state and the flash memory is too slow for the
CPU. The source of the system reset is either the external reset or the Watchdog reset.
Workaround using Rev B and Rev D
The CPU hangs after the system reset occurs. A Power Off is the only way to re-start the
system. Work around includes:
1.CPU can run at 96 MHz but the FMI clock must be configured to run at 48 MHz in the
SCU_CLKCNTR register.
2.Do not reset the STR91xF while the FMI clock frequency is above 66 MHz.
Problem will be fixed in the next revision. System reset will not reset the Flash Configuration Register.
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