ARM, RISC-V контроллеры

Про BI читали? When RXD0 is held in the spacing state (all 0’s) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Framing Error (FE) When the stop bit of a received character is a logic 0, a framing error occurs. An U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART0 RBR FIFO. Break Interrupt (BI) When RXD0 is held in the spacing state (all 0’s) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD0 goes to marking state (all 1’s). An U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0]. Note: The break interrupt is associated with the character at the top of the UART0 RBR FIFO.