ARM, RISC-V контроллеры

Всем откликнувшимся спасибо! Докладываю. Решил проблему. Перед рестартом ADC1 -> DMA2, нужно сбросить и вновь установить бит ADC1->CR2.DMA. Так у меня сейчас выглядит кусок кода перезапускающий ADC1->CR2. DMA2->HIFCR = DMA_HIFCR_AllStream4_clear; DMA2_Stream4->NDTR = NumberUseChanelADC1; ADC1->CR2 &= ~ADC_CR2_DMA; ADC1->SR &= ~ADC_SR_STRT; DMA2_Stream4->CR |= DMA_SxCR_EN; ADC1->CR2 |= (ADC_CR2_SWSTART | ADC_CR2_DMA); +============================================================================================ Разбираясь, вот что я потом прочитал. Но у меня нет переполнения!!! У меня ADC1->SR.OVR = 0. RM0385. Reference manual page 425. 15.8.1 Using the DMA Если есть overrun - the OVR bit in the ADC_SR register is set. It is then necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred to the right memory location. "When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have been transferred, which means that all the data transferred to the RAM can be considered as valid. At the end of the last DMA transfer (number of transfers configured in the DMA controller’s DMA_SxNTR register): • No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is not cleared by hardware. It must be written to 0, then to 1 to start a new transfer. • Requests can continue to be generated if the DDS bit is set to 1. This allows configuring the DMA in double-buffer circular mode." Если есть overrun - the OVR bit in the ADC_SR register is set. It is then necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred to the right memory location.