Микроконтроллеры PIC

6.2.2.1 TRAP PRIORITY AND HARD TRAP CONFLICTS If a higher priority trap occurs while any lower priority trap is in progress, processing of the lower-priority trap is suspended. The higher priority trap is acknowledged and processed. The lower priority trap remains pending until processing of the higher priority trap completes. Each hard trap that occurs must be acknowledged before code execution of any type can continue. If a lower priority hard trap occurs while a higher priority trap is pending, acknowledged or is being processed, a hard-trap conflict occurs because the lower priority trap cannot be acknowledged until processing for the higher priority trap completes. The device is automatically reset in a hard-trap conflict condition. The Trap Reset Flag (TRAPR) status bit in the Reset Control Register (RCON<15> in the Reset module) is set when the Reset occurs so that the condition can be detected in software