ARM, RISC-V контроллеры

example /***************************************************************************** * Copyright (c) 2001, 2002 Rowley Associates Limited. * * * * This file may be distributed under the terms of the License Agreement * * provided with this software. * * * * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * *****************************************************************************/ /* * Enable copying and re-mapping of interrupt vectors from User FLASH to * SRAM. If undefined, interrupt vectors will be mapped in User FLASH. * * #define SRAM_EXCEPTIONS * */ .section .vectors, "ax" .code 32 .align 0 /***************************************************************************** * Exception Vectors * *****************************************************************************/ _vectors: ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ .word 0xB9205F84 /* boot loader checksum */ ldr pc, [pc, #-0xFF0] ldr pc, [pc, #fiq_handler_address - . - 8]