ARM, RISC-V контроллеры

так вот в CW сделано (ну и наверно похоже у ИАР) .section .vectors, "ax" .code 32 .align 0 /***************************************************************************** * Exception Vectors * *****************************************************************************/ _vectors: ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ .word 0xB8A06F60 /* boot loader checksum */ ldr pc, [pc, #irq_handler_address - . - 8] ldr pc, [pc, #fiq_handler_address - . - 8] reset_handler_address: .word reset_handler undef_handler_address: .word undef_handler swi_handler_address: .word swi_handler pabort_handler_address: .word pabort_handler dabort_handler_address: .word dabort_handler irq_handler_address: .word irq_handler fiq_handler_address: .word fiq_handler собственно после того как это в SRAM разместите (какой-то регистр) нужно в С (long *)irq_handler=my_irq_handler;