ARM, RISC-V контроллеры

dsPIC33CK то же самое - 19 циклов. DIVIDE SUPPORT The dsPIC33/PIC24 Enhanced CPU supports the following types of division operations: • DIVF: 16/16 signed fractional divide (dsPIC33E devices only) • DIV.SD: 32/16 signed divide • DIV.UD: 32/16 unsigned divide • DIV.SW: 16/16 signed divide • DIV.UW: 16/16 unsigned divide The quotient for all divide instructions is placed in Working register, W0. The remainder is placed in W1. The 16-bit divisor can be located in any W register. A 16-bit dividend can be located in any W register and a 32-bit dividend must be located in an adjacent pair of W registers. All divide instructions are iterative operations and must be executed 18 times within a REPEAT loop. The developer is responsible for programming the REPEAT instruction. A complete divide operation takes 19 instruction cycles to execute. The divide flow is interruptible, just like any other REPEAT loop. All data is restored into the respective data registers after each iteration of the loop, so the user application is responsible for saving the appropriate W registers in the ISR. Although they are important to the divide hardware, the intermediate values in the W registers have no meaning to the user application. The divide instructions must be executed 18 times in a REPEAT loop to produce a meaningful result. A divide-by-zero error generates a math error trap. This condition is indicated by the Arithmetic Error Status (DIV0ERR) bit (INTCON1[6] in the interrupt controller). For more information and programming examples for the divide instructions, refer to the “16-Bit MCU and DSC Programmer’s Reference Manual” (DS70000157