Программируемая логика и ЦОС

Lattice [CrossLink-NX] 28 nm FD-SOI, FLASH, и [полукастомный RISC-V] (аж две штуки) -> Гении!!! http://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX
Из ДШ 2.8. ALUREG The CrossLink-NX family provides up to two ALUREG hard IP blocks. The ALUREG consists of an arithmetic and logical unit (ALU) and a register file. The ALU provides the functions of the RISC-V 32-bit integer base instructions with multiplier-only support for the M-extension. The divider function of the M-extension is not supported, instead the ALU provides flag outputs to enable multi-cycle division/remainder operations to be implemented in soft logic. Custom operations rotate left/right and 32-bit fixed point multiplication have also been added to the ALU. All the functions of the ALU are completed in one clock cycle. Input and output registers are available and can be separately bypassed through configuration. The register file consists of 32-bit registers. The register file provides a single write port and two read ports which can be accessed simultaneously.