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Evgeny_CD, Архитектор (15.02.2020 02:29 - 02:36, просмотров: 556) ответил dxwak на [LPC5500 Series] World’s First Arm® Cortex® -M33 for Mass Market Leveraging 40nm Sampling Now
Из приятного: --The DMA supports GPIO ports. -- Programmable Logic Unit (PLU) to create small combinatorial and/or sequential logic networks including state machines. The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table (LUT) elements, and four flip-flops. -- A tool suite is provided to facilitate programming of the PLU to implement the logic network described in a Verilog RTL design. -- High-Speed SPI interface (Flexcomm Interface 8) 50Мбит мастер и слейв -- the maximum supported bit rate for USART master and slave synchronous mode is 10 Mbit/s. -- the maximum supported bit rate for USART master and slave asynchronous mode is 6.25 Mbit/s. -- АЦП 16b вполне приличный по динамическому диапазону и погрешностям.