Схемы, платы, компоненты

процедуру сброса шины, вероятно, не делал 

UM10204.pdf

3.1.16 Bus clear

In the unlikely event where the clock (SCL) is stuck LOW, the preferential procedure is

to reset the bus using the HW reset signal if your I2C devices have HW reset inputs. If

the I2C devices do not have HW reset inputs, cycle power to the devices to activate the

mandatory internal Power-On Reset (POR) circuit.

If the data line (SDA) is stuck LOW, the controller should send nine clock pulses. The

device that held the bus LOW should release it sometime within those nine clocks. If not,

then use the HW reset or cycle power to clear the bus.

вот в DS на EEPROM несколько вариантов "Software reset" описано

br24axxxf-wlb-e.pdf