SM (24.05.2005 14:16, просмотров: 1) ответил zx на подскажите, кроме ISTR и регистровс адресами 2C00...2C1F какие-то ещё регистры нужно установить для инициации McBSP1Ответ: Ну во первый проинитить все PLL'ские дела и системные клоки корректно распустить. А ISTR он вообще read-only, как это его Вы инитить задумали? Вот мой инит целиком (под кодек AIC23) - он точно рабочий.
CODEC_CTL: .macro adr,data
mov adr << #9, ac0
or data,ac0
call send_spi
.endm
start:
; ----------- Set new interrupt vector's location
bset intm
bclr C54CM
bclr ARMS
bclr CPL
rpt #20
nop
mov #0, port(#PLLCSR)
rpt #20
nop
amov #3FFFh,xsp
amov #3EFFh,xssp
rpt #20
nop
mov #vecs>>8,mmap(@IVPD)
mov #vecs>>8,mmap(@IVPH)
rpt #20
nop
; ----------- Reset CPU for dual stack with fast return configuration
reset
nop
nop
nop
nop
nop
nop
nop
nop
halt: b halt
begin:
amov #usrstack+STACKSIZE-2,xsp
amov #sysstack+STACKSIZE-2,xssp
bclr C54CM
bclr ARMS
bclr CPL
; PLL
mov #8000h,port(#PLLDIV1)
mov #8003h,port(#PLLDIV2)
mov #10,port(#PLLM)
rpt #20
nop
mov #1, port(#PLLCSR)
wait_lock: rpt #20
nop
mov port(#PLLCSR),t0
and #20h,t0
bcc wait_lock,t0==#0
; timer (12.288 MHZ TOUT1 for codec)
mov #0,port(#GPTGCTL_1)
mov #0,port(#GPTGCTL_0)
mov #0,port(#GPTCTL1_1)
mov #0,port(#GPTCTL1_0)
rpt #100
nop
mov #10h,port(#TSSR)
mov #0003h, port(#GPTGCTL_1)
mov #11,port(#GPTPRD1_1)
mov #0,port(#GPTPRD2_1)
mov #0,port(#GPTPRD3_1)
mov #0,port(#GPTPRD4_1)
mov #0,port(#GPTCNT1_1)
mov #0,port(#GPTCNT2_1)
mov #0,port(#GPTCNT3_1)
mov #0,port(#GPTCNT4_1)
mov #0088h, port(#GPTCTL1_1)
mov #0003h, port(#GPTGCTL_0)
mov #2944*2,port(#GPTPRD1_0)
mov #0,port(#GPTPRD2_0)
mov #0,port(#GPTPRD3_0)
mov #0,port(#GPTPRD4_0)
mov #0,port(#GPTCNT1_0)
mov #0,port(#GPTCNT2_0)
mov #0,port(#GPTCNT3_0)
mov #0,port(#GPTCNT4_0)
mov #0080h, port(#GPTCTL1_0)
; HPI - as GPIO
mov #0,port(#XBSR)
rpt #3
nop
mov #0FF0h, port(#PGPIOEN2)
mov #0, port(#PGPIODIR2)
;76543210
mov #11110000b, port(#IODIR)
mov #01110000b, port(#IODATA)
; MCBSP #0 - SPI, codec control
mov #0, port(#SPCR1_0) ; RRST=0
and #0, port(#SPCR2_0) ; XRST=0, GRST=0, frst=0
rpt #100h
nop
mov #1800h,port(#SPCR1_0)
mov #0,port(#SPCR2_0)
mov #0b09h,port(#PCR0) ; 0b09
mov #0040h,port(#RCR1_0)
mov #1,port(#RCR2_0) ;
mov #0040h,port(#XCR1_0)
mov #1,port(#XCR2_0) ;
mov #1314h,port(#SRGR1_0) ; 00FF
mov #2000h,port(#SRGR2_0)
mov #0,port(#MCR1_0)
mov #0,port(#MCR2_0)
or #0C0h,port(#SPCR2_0) ; enable SR generator
rpt #0F000h
nop ; wait for >=2 SR periods
or #1,port(#SPCR2_0)
or #1,port(#SPCR1_0)
rpt #0F000h
nop ; wait for >=2 SR periods
CODEC_CTL #0Fh,#0h
rpt #0F000h
nop ; wait for >=2 SR periods
CODEC_CTL #0Fh,#0h
rpt #0F000h
nop ; wait for >=2 SR periods
CODEC_CTL #0Fh,#0h
rpt #0F000h
nop ; wait for >=2 SR periods
CODEC_CTL #0,#01Ch
CODEC_CTL #1,#01Ch
CODEC_CTL #2,#0F9h
CODEC_CTL #3,#0F9h
CODEC_CTL #4,#012h ; 015
CODEC_CTL #5,#000h ;002h
CODEC_CTL #6,#100h
CODEC_CTL #7,#053h ; 13h for slave
CODEC_CTL #8,#018h
CODEC_CTL #9,#001h
; I2C
mov #0,port(#I2CMDR)
mov #0,port(#DMA_CCR2)
rpt #1000
nop
mov #7,port(#I2CPSC) ; 294.942/4/8= 9.216 MHZ module clock
mov #7,port(#I2CCLKL)
mov #7,port(#I2CCLKH) ; 9.216/(7+5+7+5) = 384 kHz
mov #050h,port(#I2CSAR) ; slave address
rpt #10
nop
mov #20h,port(#I2CMDR) ; out from reset
rpt #10
nop
mov #6,port(#I2CIER)
CSDP_TX: .set 0000011001000000b
CSDP_TXW: .set 0000011001000001b
CSDP_RX: .set 0010000000001100b
CCR_TX: .set 0001011000010100b
CCR_RX: .set 0100011000010011b
; I2C DMAC
;fedcba9876543210
mov #CCR_TX, port(#DMA_CCR2)
mov #0000000000100000b, port(#DMA_CICR2)
mov #CSDP_TX, port(#DMA_CSDP2)
mov #0, port(#DMA_CSSA_U2)
mov #0, port(#DMA_CDSA_U2)
mov #2, port(#DMA_CEN2)
mov #1, port(#DMA_CFN2)
; UART
mov #0,port(#URPECR)
rpt #100
nop
mov #8000h,port(#URPECR)
rpt #10
nop
mov #3,port(#URLCR)
rpt #5
nop
mov #80,port(#URDLL)
mov #0,port(#URDLM)
mov #1,port(#URIER)
mov #8,port(#URFCR)
mov port(#URLSR),t0
rpt #15
mov port(#URRBR),t0
mov #30h,port(#URTHR)
rpt #0F000h
nop
; MCBSP #1 - codec data
mov #0, port(#SPCR1_1) ; RRST=0
and #0, port(#SPCR2_1) ; XRST=0, GRST=0, frst=0
rpt #100h
nop
mov #0000h,port(#SPCR1_1)
mov #0000h,port(#SPCR2_1)
mov #0003h,port(#PCR1) ; 0b09
mov #0140h,port(#RCR1_1)
mov #0001h,port(#RCR2_1) ;
mov #0140h,port(#XCR1_1)
mov #0001h,port(#XCR2_1) ;
mov #0047h,port(#SRGR1_1) ; 00FF
mov #0000h,port(#SRGR2_1)
mov #0000h,port(#MCR1_1)
mov #0000h,port(#MCR2_1)
rpt #1000
nop
; rpt #0F000h
; nop
; DMAC's
; #0 - RX
;fedcba9876543210
mov #0100011101000101b, port(#DMA_CCR0)
mov #0000000000000000b, port(#DMA_CICR0)
mov #0000000000001101b, port(#DMA_CSDP0)
mov #(DRR1_1 << 1) & 0FFFFh, port(#DMA_CSSA_L0)
mov #(DRR1_1 >> 15) , port(#DMA_CSSA_U0)
mov #(RXBUF << 1) & 0FFFFh, port(#DMA_CDSA_L0)
mov #(RXBUF >> 15) , port(#DMA_CDSA_U0)
mov #BUFSZ*2, port(#DMA_CEN0)
mov #2, port(#DMA_CFN0)
; #1 - TX
;fedcba9876543210
mov #0001011101000110b, port(#DMA_CCR1)
mov #0000000000101000b, port(#DMA_CICR1)
mov #0000011000000001b, port(#DMA_CSDP1)
mov #(TXBUF << 1) & 0FFFFh, port(#DMA_CSSA_L1)
mov #(TXBUF >> 15) , port(#DMA_CSSA_U1)
mov #(DXR1_1 << 1) & 0FFFFh, port(#DMA_CDSA_L1)
mov #(DXR1_1 >> 15) , port(#DMA_CDSA_U1)
mov #BUFSZ*2, port(#DMA_CEN1)
mov #2, port(#DMA_CFN1)
rpt #200h
nop
or #80h,port(#DMA_CCR0)
or #80h,port(#DMA_CCR1)
rpt #200h
nop
btst #0,port(#DMA_CSR1),TC1
btst #0,port(#DMA_CSR0),TC1
mov #0FFFFh,mmap(@IFR0)
mov #0FFFFh,mmap(@IFR1)
or #1,port(#SPCR2_1)
or #1,port(#SPCR1_1)
mov #1210h, mmap(@IER0)
mov #0094h, mmap(@IER1)
bclr intm
.................................
send_spi: btst #1,port(#SPCR2_0),TC1
bcc send_spi,!TC1
mov ac0,port(#DXR1_0)
ret
-
- ??? zx(206 знак., 24.05.2005 15:15,
)
- Ответ: SM(4221 знак., 24.05.2005 15:19,
)
- ошибка при компиляции zx(231 знак., 24.05.2005 15:52, )
- ошибка при компиляции zx(231 знак., 24.05.2005 15:52,
- Ответ: SM(4221 знак., 24.05.2005 15:19,
- ??? zx(206 знак., 24.05.2005 15:15,