Микроконтроллеры AVR

; DDN Research [ http://ddn.at.ua/] ; DiAVR Generated Assembler Listing ; Date: 03-14-2018 || Time: 12:24:17 ; Search File: D:\роб стол\розраб\taho_m8.hex ; ; 0x0: rjmp +0x2E ;Relative Jump PC<-PC + k +1, send to 0x30 0x2: rjmp -0x4 ;Relative Jump PC<-PC + k +1, send to 0x0 0x4: rjmp -0x6 ;Relative Jump PC<-PC + k +1, send to 0x0 0x6: rjmp -0x8 ;Relative Jump PC<-PC + k +1, send to 0x0 0x8: rjmp -0xA ;Relative Jump PC<-PC + k +1, send to 0x0 0xA: rjmp -0xC ;Relative Jump PC<-PC + k +1, send to 0x0 0xC: rjmp -0xE ;Relative Jump PC<-PC + k +1, send to 0x0 0xE: rjmp -0x10 ;Relative Jump PC<-PC + k +1, send to 0x0 0x10: rjmp -0x12 ;Relative Jump PC<-PC + k +1, send to 0x0 0x12: rjmp -0x14 ;Relative Jump PC<-PC + k +1, send to 0x0 0x14: rjmp -0x16 ;Relative Jump PC<-PC + k +1, send to 0x0 0x16: rjmp -0x18 ;Relative Jump PC<-PC + k +1, send to 0x0 0x18: rjmp -0x1A ;Relative Jump PC<-PC + k +1, send to 0x0 0x1A: rjmp -0x1C ;Relative Jump PC<-PC + k +1, send to 0x0 0x1C: rjmp -0x1E ;Relative Jump PC<-PC + k +1, send to 0x0 0x1E: rjmp -0x20 ;Relative Jump PC<-PC + k +1, send to 0x0 0x20: rjmp -0x22 ;Relative Jump PC<-PC + k +1, send to 0x0 0x22: rjmp -0x24 ;Relative Jump PC<-PC + k +1, send to 0x0 0x24: rjmp -0x26 ;Relative Jump PC<-PC + k +1, send to 0x0 0x26: ;FLASH information - NO command 0x28: ;FLASH information - NO command 0x2A: ;FLASH information - NO command 0x2C: ;FLASH information - NO command 0x2E: ;FLASH information - NO command 0x30: cli ;no comments 0x32: eor r30, r30 ;Exclusive OR Registers Rd <- Rd ffl Rr ; equivalent function = clr r1006 ;Clear Register Rd <- Rd ffi Rd 0x34: out 0x1C, r30 ;Out Port P<-Rr 0x36: ldi r15, r1 ;Load Immediate Rd <-K 0x38: out 0x3B, r31 ;Out Port P<-Rr 0x3A: out 0x3B, r30 ;Out Port P<-Rr 0x3C: out 0x35, r30 ;Out Port P<-Rr 0x3E: ldi r31, r8 ;Load Immediate Rd <-K 0x40: out 0x21, r31 ;Out Port P<-Rr 0x42: out 0x21, r30 ;Out Port P<-Rr 0x44: ldi r8, r13 ;Load Immediate Rd <-K 0x46: ldi r10, r2 ;Load Immediate Rd <-K 0x48: eor r27, r27 ;Exclusive OR Registers Rd <- Rd ffl Rr ; equivalent function = clr r955 ;Clear Register Rd <- Rd ffi Rd 0x4A: st X+, r30 ;Load Indirect ;Store Indirect 0x4C: dec r24 ;Decrement Rd <- Rd - 1 0x4E: brbc 0x1, -0x6 ;Branch if Status Flag Cleared => if (SREG(Z)=0) then goto 0x4A Equivalent: breq -0x6 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x50: ldi r8, r0 ;Load Immediate Rd <-K 0x52: ldi r9, r4 ;Load Immediate Rd <-K 0x54: ldi r10, r16 ;Load Immediate Rd <-K 0x56: st X+, r30 ;Load Indirect ;Store Indirect 0x58: sbiw r24, 0x1 ;Subtract Immediate from Word Rdh:Rdl <- Rdh:Rdl - K 0x5A: brbc 0x1, -0x6 ;Branch if Status Flag Cleared => if (SREG(Z)=0) then goto 0x56 Equivalent: breq -0x6 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x5C: ldi r14, r24 ;Load Immediate Rd <-K 0x5E: ldi r15, r0 ;Load Immediate Rd <-K 0x60: push r24, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x62: push r25, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x64: sbiw r24, 0x0 ;Subtract Immediate from Word Rdh:Rdl <- Rdh:Rdl - K 0x66: brbs 0x1, +0x18 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x80 Equivalent: breq +0x18 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x68: push r26, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x6A: push r27, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x6C: push r0, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x6E: push r1, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x70: movw r22, r30 ;Copy Register Word Rd+1:Rd<-Rr+1:Rr 0x72: movw r30, r0 ;Copy Register Word Rd+1:Rd<-Rr+1:Rr 0x74: push r0, Z+ ;Load Program Memory and Post-lnc Rd <- (Z), Z <- Z+1 0x76: st X+, r0 ;Load Indirect ;Store Indirect 0x78: sbiw r24, 0x1 ;Subtract Immediate from Word Rdh:Rdl <- Rdh:Rdl - K 0x7A: brbc 0x1, -0x8 ;Branch if Status Flag Cleared => if (SREG(Z)=0) then goto 0x74 Equivalent: breq -0x8 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x7C: movw r30, r22 ;Copy Register Word Rd+1:Rd<-Rr+1:Rr 0x7E: rjmp -0x20 ;Relative Jump PC<-PC + k +1, send to 0x60 0x80: ldi r30, r15 ;Load Immediate Rd <-K 0x82: out 0x3D, r30 ;Out Port P<-Rr 0x84: ldi r14, r4 ;Load Immediate Rd <-K 0x86: out 0x3E, r30 ;Out Port P<-Rr 0x88: ldi r12, r16 ;Load Immediate Rd <-K 0x8A: ldi r13, r1 ;Load Immediate Rd <-K 0x8C: rjmp +0xD4 ;Relative Jump PC<-PC + k +1, send to 0x162 0x8E: ldi r30, r0 ;Load Immediate Rd <-K 0x90: ldi r15, r7 ;Load Immediate Rd <-K 0x92: rcall +0x294 ;Relative Subroutine Call, me goto: 0x1BA 0x94: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x98 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x96: sbi 0x18, 0x0 ;Set Bit in I/O Register l/O(P,b) <-1 0x98: ldi r14, r24 ;Load Immediate Rd <-K 0x9A: ldi r15, r3 ;Load Immediate Rd <-K 0x9C: rcall +0x284 ;Relative Subroutine Call, me goto: 0x1BA 0x9E: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xA2 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xA0: sbi 0x12, 0x7 ;Set Bit in I/O Register l/O(P,b) <-1 0xA2: ldi r30, r11 ;Load Immediate Rd <-K 0xA4: ldi r15, r2 ;Load Immediate Rd <-K 0xA6: rcall +0x274 ;Relative Subroutine Call, me goto: 0x1BA 0xA8: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xAC Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xAA: sbi 0x12, 0x6 ;Set Bit in I/O Register l/O(P,b) <-1 0xAC: ldi r30, r20 ;Load Immediate Rd <-K 0xAE: ldi r15, r1 ;Load Immediate Rd <-K 0xB0: rcall +0x264 ;Relative Subroutine Call, me goto: 0x1BA 0xB2: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xB6 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xB4: sbi 0x12, 0x5 ;Set Bit in I/O Register l/O(P,b) <-1 0xB6: ldi r30, r0 ;Load Immediate Rd <-K 0xB8: ldi r15, r1 ;Load Immediate Rd <-K 0xBA: rcall +0x254 ;Relative Subroutine Call, me goto: 0x1BA 0xBC: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xC0 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xBE: sbi 0x18, 0x7 ;Set Bit in I/O Register l/O(P,b) <-1 0xC0: ldi r14, r13 ;Load Immediate Rd <-K 0xC2: ldi r15, r1 ;Load Immediate Rd <-K 0xC4: rcall +0x244 ;Relative Subroutine Call, me goto: 0x1BA 0xC6: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xCA Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xC8: sbi 0x18, 0x6 ;Set Bit in I/O Register l/O(P,b) <-1 0xCA: ldi r30, r14 ;Load Immediate Rd <-K 0xCC: ldi r15, r1 ;Load Immediate Rd <-K 0xCE: rcall +0x234 ;Relative Subroutine Call, me goto: 0x1BA 0xD0: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xD4 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xD2: sbi 0x12, 0x4 ;Set Bit in I/O Register l/O(P,b) <-1 0xD4: ldi r30, r26 ;Load Immediate Rd <-K 0xD6: ldi r15, r0 ;Load Immediate Rd <-K 0xD8: rcall +0x224 ;Relative Subroutine Call, me goto: 0x1BA 0xDA: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xDE Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xDC: sbi 0x12, 0x3 ;Set Bit in I/O Register l/O(P,b) <-1 0xDE: ldi r30, r14 ;Load Immediate Rd <-K 0xE0: ldi r15, r0 ;Load Immediate Rd <-K 0xE2: rcall +0x214 ;Relative Subroutine Call, me goto: 0x1BA 0xE4: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xE8 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xE6: sbi 0x12, 0x2 ;Set Bit in I/O Register l/O(P,b) <-1 0xE8: ldi r14, r8 ;Load Immediate Rd <-K 0xEA: ldi r15, r0 ;Load Immediate Rd <-K 0xEC: rcall +0x204 ;Relative Subroutine Call, me goto: 0x1BA 0xEE: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xF2 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xF0: sbi 0x12, 0x1 ;Set Bit in I/O Register l/O(P,b) <-1 0xF2: ldi r30, r21 ;Load Immediate Rd <-K 0xF4: ldi r15, r0 ;Load Immediate Rd <-K 0xF6: rcall +0x194 ;Relative Subroutine Call, me goto: 0x1BA 0xF8: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xFC Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0xFA: sbi 0x12, 0x0 ;Set Bit in I/O Register l/O(P,b) <-1 0xFC: ldi r14, r23 ;Load Immediate Rd <-K 0xFE: ldi r15, r0 ;Load Immediate Rd <-K 0x100: rcall +0x184 ;Relative Subroutine Call, me goto: 0x1BA 0x102: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x106 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x104: sbi 0x15, 0x5 ;Set Bit in I/O Register l/O(P,b) <-1 0x106: ldi r30, r10 ;Load Immediate Rd <-K 0x108: ldi r15, r0 ;Load Immediate Rd <-K 0x10A: rcall +0x174 ;Relative Subroutine Call, me goto: 0x1BA 0x10C: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x110 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x10E: sbi 0x15, 0x4 ;Set Bit in I/O Register l/O(P,b) <-1 0x110: ldi r14, r15 ;Load Immediate Rd <-K 0x112: ldi r15, r0 ;Load Immediate Rd <-K 0x114: rcall +0x164 ;Relative Subroutine Call, me goto: 0x1BA 0x116: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x11A Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x118: sbi 0x15, 0x3 ;Set Bit in I/O Register l/O(P,b) <-1 0x11A: ldi r14, r5 ;Load Immediate Rd <-K 0x11C: ldi r15, r0 ;Load Immediate Rd <-K 0x11E: rcall +0x154 ;Relative Subroutine Call, me goto: 0x1BA 0x120: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x124 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x122: sbi 0x15, 0x2 ;Set Bit in I/O Register l/O(P,b) <-1 0x124: ldi r30, r29 ;Load Immediate Rd <-K 0x126: ldi r15, r0 ;Load Immediate Rd <-K 0x128: rcall +0x144 ;Relative Subroutine Call, me goto: 0x1BA 0x12A: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x12E Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x12C: sbi 0x15, 0x1 ;Set Bit in I/O Register l/O(P,b) <-1 0x12E: ldi r30, r22 ;Load Immediate Rd <-K 0x130: ldi r15, r0 ;Load Immediate Rd <-K 0x132: rcall +0x134 ;Relative Subroutine Call, me goto: 0x1BA 0x134: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x138 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x136: sbi 0x15, 0x0 ;Set Bit in I/O Register l/O(P,b) <-1 0x138: ldi r14, r31 ;Load Immediate Rd <-K 0x13A: ldi r15, r0 ;Load Immediate Rd <-K 0x13C: rcall +0x124 ;Relative Subroutine Call, me goto: 0x1BA 0x13E: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x142 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x140: sbi 0x18, 0x5 ;Set Bit in I/O Register l/O(P,b) <-1 0x142: ldi r14, r25 ;Load Immediate Rd <-K 0x144: ldi r15, r0 ;Load Immediate Rd <-K 0x146: rcall +0x114 ;Relative Subroutine Call, me goto: 0x1BA 0x148: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x14C Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x14A: sbi 0x18, 0x4 ;Set Bit in I/O Register l/O(P,b) <-1 0x14C: ldi r14, r20 ;Load Immediate Rd <-K 0x14E: ldi r15, r0 ;Load Immediate Rd <-K 0x150: rcall +0x104 ;Relative Subroutine Call, me goto: 0x1BA 0x152: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x156 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x154: sbi 0x18, 0x3 ;Set Bit in I/O Register l/O(P,b) <-1 0x156: ldi r30, r15 ;Load Immediate Rd <-K 0x158: ldi r15, r0 ;Load Immediate Rd <-K 0x15A: rcall +0x94 ;Relative Subroutine Call, me goto: 0x1BA 0x15C: brbs 0x0, +0x2 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x160 Equivalent: brcs +0x2 ;Branch if Carry Set if(C=1)thenPC<-PC + k+1 0x15E: sbi 0x18, 0x2 ;Set Bit in I/O Register l/O(P,b) <-1 0x160: ret ;no comments 0x162: ldi r30, r29 ;Load Immediate Rd <-K 0x164: out 0x17, r30 ;Out Port P<-Rr 0x166: ldi r30, r31 ;Load Immediate Rd <-K 0x168: out 0x14, r30 ;Out Port P<-Rr 0x16A: ser r30 ;Set Register Rd<-$FF 0x16C: out 0x11, r30 ;Out Port P<-Rr 0x16E: ldi r14, r0 ;Load Immediate Rd <-K 0x170: out 0x8, r30 ;Out Port P<-Rr 0x172: mov r26, r7 ;Move Between Registers Rd<-Rr 0x174: ldi r14, r0 ;Load Immediate Rd <-K 0x176: rcall +0x72 ;Relative Subroutine Call, me goto: 0x1C0 0x178: mov r0, r30 ;Move Between Registers Rd<-Rr 0x17A: ldi r10, r0 ;Load Immediate Rd <-K 0x17C: sbic 0x1, r 0x6 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3 0x17E: ldi r10, r1 ;Load Immediate Rd <-K 0x180: ldi r14, r1 ;Load Immediate Rd <-K 0x182: rcall +0x60 ;Relative Subroutine Call, me goto: 0x1C0 0x184: tst r30, r0 ;Test for Zero or Minus Rd <- Rd . Rd ; equivalent function = and r30, r0 ;Logical AND Registers Rd <- Rd . Rr 0x186: brbs 0x1, +0x4 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x18C Equivalent: breq +0x4 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x188: ldi r14, r1 ;Load Immediate Rd <-K 0x18A: mov r6, r30 ;Move Between Registers Rd<-Rr 0x18C: ldi r14, r0 ;Load Immediate Rd <-K 0x18E: sbic 0x1, r 0x6 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3 0x190: ldi r14, r1 ;Load Immediate Rd <-K 0x192: mov r7, r30 ;Move Between Registers Rd<-Rr 0x194: ldi r14, r1 ;Load Immediate Rd <-K 0x196: cp r30, r6 ;Rotate Left Through Carry Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7) 0x198: brbc 0x1, +0x10 ;Branch if Status Flag Cleared => if (SREG(Z)=0) then goto 0x1AA Equivalent: breq +0x10 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x19A: eor r6, r6 ;Exclusive OR Registers Rd <- Rd ffl Rr ; equivalent function = clr r102 ;Clear Register Rd <- Rd ffi Rd 0x19C: ldi r14, r0 ;Load Immediate Rd <-K 0x19E: out 0x12, r30 ;Out Port P<-Rr 0x1A0: out 0x15, r30 ;Out Port P<-Rr 0x1A2: out 0x18, r30 ;Out Port P<-Rr 0x1A4: rcall -0x280 ;Relative Subroutine Call, me goto: 0x8E 0x1A6: eor r4, r4 ;Exclusive OR Registers Rd <- Rd ffl Rr ; equivalent function = clr r68 ;Clear Register Rd <- Rd ffi Rd 0x1A8: eor r5, r5 ;Exclusive OR Registers Rd <- Rd ffl Rr ; equivalent function = clr r85 ;Clear Register Rd <- Rd ffi Rd 0x1AA: ldi r24, r1 ;Load Immediate Rd <-K 0x1AC: dec r24 ;Decrement Rd <- Rd - 1 0x1AE: brbc 0x1, -0x4 ;Branch if Status Flag Cleared => if (SREG(Z)=0) then goto 0x1AC Equivalent: breq -0x4 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x1B0: movw r30, r4 ;Copy Register Word Rd+1:Rd<-Rr+1:Rr 0x1B2: adiw r30, 0x1 ;Add Immediate to Word Rdh:Rdl<-Rdh:Rdl+K 0x1B4: movw r4, r30 ;Copy Register Word Rd+1:Rd<-Rr+1:Rr 0x1B6: rjmp -0x46 ;Relative Jump PC<-PC + k +1, send to 0x172 0x1B8: rjmp -0x2 ;Relative Jump PC<-PC + k +1, send to 0x1B8 - Maiby, this is a Stop Program 0x1BA: cp r30, r4 ;Rotate Left Through Carry Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7) 0x1BC: cpc r31, r5 ;Compare with Carry Rd-Rr-C 0x1BE: ret ;no comments 0x1C0: cp r30, r26 ;Rotate Left Through Carry Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7) 0x1C2: ldi r14, r1 ;Load Immediate Rd <-K 0x1C4: brbs 0x1, +0x2 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1C8 Equivalent: breq +0x2 ;Branch if Equal if(Z=1)thenPC<-PC + k + 1 0x1C6: eor r30, r30 ;Exclusive OR Registers Rd <- Rd ffl Rr ; equivalent function = clr r1006 ;Clear Register Rd <- Rd ffi Rd 0x1C8: ret ;no comments