Программируемая логика и ЦОС

module freq_divider (
    input wire clk_in,
    output wire clk_out_10,
    output wire clk_out_100,
    output wire clk_out_1000
);

reg [3:0] count_10;
reg [6:0] count_100;
reg [9:0] count_1000;

always @(posedge clk_in) begin
    count_10 <= count_10 + 1;
    count_100 <= count_100 + 1;
    count_1000 <= count_1000 + 1;

    if (count_10 == 5'd4) begin
        count_10 <= 0;
        clk_out_10 <= ~clk_out_10;
    end

    if (count_100 == 7'd99) begin
        count_100 <= 0;
        clk_out_100 <= ~clk_out_100;
    end

    if (count_1000 == 10'd999) begin
        count_1000 <= 0;
        clk_out_1000 <= ~clk_out_1000;
    end
end
endmodule