ARM, RISC-V контроллеры

В даташите как-то коряво написано: 

When carrying out FLASH-related operations, it is strongly recommended that the system main frequency

is not greater than 120M.

If the actual application must require the use of system mains frequency greater than 120M, it should be noted

that:

In the non-zero-wait area FLASH and zero-wait area FLASH, user word read/write and vendor configuration

word and Boot area read, the following operations need to be done, firstly, HCLK is divided into two (Related

peripheral clocks are also divided at the same time, the impact needs to be evaluated), and then restored after

the FLASH operation is completed to ensure that the FLASH access clock frequency does not exceed 60Mhz

(FLASH_ CTLR register bit[25]-SCKMOD can configure FLASH access clock frequency as system clock or

half of system clock, the default configuration of this bit is half of system clock).

Т.е. явно пишут, что надо убавлять до 60МГц именно HCLK (при этом учитывать что частота снизится и для периферии!!!).

Ну и вскользь упоминают про делитель в регистре FLASH_ CTLR. Причем пишут, что на входе у делителя SYSCLK !!! Без бутылки не разберешься.