ARM, RISC-V контроллеры

Выкладываю исходные тексты Cstartup-ов: Вот исходник CStartup_SAM7.c - ничего кроме комменторования Board.h не изменял. //*---------------------------------------------------------------------------- //* ATMEL Microcontroller Software Support - ROUSSET - //*---------------------------------------------------------------------------- //* File Name : Cstartup_SAM7.c //* Object : Low level initializations for RNTIG10 //* Creation : 12/Jun/04 (by Atmel) //* Modified : 18/Mar/05 (by TNS) //*---------------------------------------------------------------------------- // Include the board file description //#include "Board.h" #include "Cstartup_SAM7.h" // The following functions must be write in ARM mode this function called directly // by exception vector extern void AT91F_Spurious_handler(void); extern void AT91F_Default_IRQ_handler(void); extern void AT91F_Default_FIQ_handler(void); //*---------------------------------------------------------------------------- //* \fn AT91F_LowLevelInit //* \brief This function performs very low level HW initialization //* this function can be use a Stack, depending the compilation //* optimization mode //*---------------------------------------------------------------------------- void AT91F_LowLevelInit( void ) @ "ICODE" { int i; AT91PS_PMC pPMC = AT91C_BASE_PMC; //* Set Flash Waite sate Single Cycle Access at Up to 30 MHz, or 40 // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN // Ïî-ðóññêè: óñòàíàâëèâàåì íà Flash ïàìÿòü 1 WS è 50 òàêòîâ çà ìèêðîñåêóíäó AT91C_BASE_MC->MC_FMR = ( (AT91C_MC_FMCN) & ( 50 << 16 ) ) | AT91C_MC_FWS_1FWS; //* Watchdog Disable AT91C_BASE_WDTC->WDTC_WDMR = AT91C_SYSC_WDDIS; //* Set MCK at 47 923 200 //* Óñòàíàâëèâàåì MasterClock (MCK) = 47 923 200 Ãö // 1 Enabling the Main Oscillator: // SCK = 1/32768 = 30.51 uSeconde // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms // Ïî-ðóññêè: SlowClock (SCK) îò ÷àñîâîãî êâàðöà => SCK(Sec)=30.51 uS, // óñòàíàâëèâàåì Startup Time = 8 * N(=6) / SCK(=32768) = 1,46484375 mS pPMC->PMC_MOR = ( ( AT91C_CKGR_OSCOUNT & ( 0x06 << 8 ) | AT91C_CKGR_MOSCEN ) ); // Wait the startup time // Æä¸ì óñòàíîâëåíèÿ MainClock while( !( pPMC->PMC_SR & AT91C_PMC_MOSCS ) ); // 2 Checking the Main Oscillator Frequency (Optional) // Çäåñü ìîæíî ïðîâåðèòü òî÷íîñòü ÷àñòîòû ÷òåíèåì MAINF èç CKGR_MCFR, ÷òî áóäåò ðàâíî êîëè÷åñòâó òàêòîâ MainClock çà 16 òàêòîâ SCK // 3 Setting PLL and divider: // - div by 5 Fin = 3,6864 MHz =(18,432 / 5) // - Mul 25+1: Fout = 95,8464 =(3,6864 * 26) // for 96 MHz the erroe is 0.16% // Field out NOT USED = 0 // PLLCOUNT pll startup time estimate at : 0.844 ms // PLLCOUNT 28 = 0.000844 /(1/32768) // Óñòàíàâëèâàåì PLLClock íà 96 MHz â îñíîâíîì äëÿ USB pPMC->PMC_PLLR = ( ( AT91C_CKGR_DIV & 0x05 ) | ( AT91C_CKGR_PLLCOUNT & ( 28 << 8 ) ) | ( AT91C_CKGR_MUL & ( 25 << 16 ) ) ); // Wait the startup time // Æä¸ì óñòàíîâëåíèÿ PLL Clock while( !( pPMC->PMC_SR & AT91C_PMC_LOCK ) ); // 4. Selection of Master Clock and Processor Clock // select the PLL clock divided by 2 // Ïî-ðóññêè: âûáèðàåì â êà÷åñòâå MasterClock (MCK) è ProcessorClock (PCK) PLLCK ñ äåëåíèåì íà 2 pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; // Æä¸ì óñòàíîâëåíèÿ Master Clock - ïîëåçíî ïðè èçìåíåíèè ÷àñòîòû äëÿ ýêîíîìèè ïîòðåáëåíèÿ while( !( pPMC->PMC_SR & AT91C_PMC_MCKRDY ) ); // Set up the default interrupts handler vectors // Íàñòðàèâàåì àäðåñà îáðàáîò÷èêîâ ïðåðûâàíèé ïî óìîë÷àíèþ AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler; for( i = 1; i < 31; i++ ){ AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler; } AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; } Вот исходник CStartup.s79 - тоже всё родное. ;------------------------------------------------------------------------------ ;- ATMEL Microcontroller Software Support - ROUSSET - ;------------------------------------------------------------------------------ ; The software is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ;----------------------------------------------------------------------------- ;- File source : Cstartup.s79 ;- Object : Generic CStartup for IAR No Use REMAP ;- Compilation flag : None ;- ;- 1.0 15/Jun/04 JPP : Creation ;------------------------------------------------------------------------------ #include "AT91SAM7S64_inc.h" ;------------------------------------------------------------------------------ ;- Area Definition ;------------------------------------------------------------------------------ ;--------------------------------------------------------------- ; ?RESET ; Reset Vector. ; Normally, segment INTVEC is linked at address 0. ; For debugging purposes, INTVEC may be placed at other ; addresses. ; A debugger that honors the entry point will start the ; program in a normal way even if INTVEC is not at address 0. ;------------------------------------------------------------- PROGRAM ?RESET RSEG INTRAMSTART_REMAP RSEG INTRAMEND_REMAP RSEG ICODE:CODE:ROOT(2) CODE32 ; Always ARM mode after reset org 0 reset ;------------------------------------------------------------------------------ ;- Exception vectors ;-------------------- ;- These vectors can be read at address 0 or at RAM address ;- They ABSOLUTELY requires to be in relative addresssing mode in order to ;- guarantee a valid jump. For the moment, all are just looping. ;- If an exception occurs before remap, this would result in an infinite loop. ;- To ensure if a exeption occurs before start application to infinite loop. ;------------------------------------------------------------------------------ B InitReset ; 0x00 Reset handler undefvec: B undefvec ; 0x04 Undefined Instruction swivec: B swivec ; 0x08 Software Interrupt pabtvec: B pabtvec ; 0x0C Prefetch Abort dabtvec: B dabtvec ; 0x10 Data Abort rsvdvec: B rsvdvec ; 0x14 reserved irqvec: B IRQ_Handler_Entry ; 0x18 IRQ fiqvec: ; 0x1c FIQ ;------------------------------------------------------------------------------ ;- Function : FIQ_Handler_Entry ;- Treatments : FIQ Controller Interrupt Handler. ;- Called Functions : AIC_FVR[interrupt] ;------------------------------------------------------------------------------ FIQ_Handler_Entry: ;- Switch in SVC/User Mode to allow User Stack access for C code ; because the FIQ is not yet acknowledged ;- Save and r0 in FIQ_Register mov r9,r0 ldr r0 , [r8, #AIC_FVR] msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC ;- Save scratch/used registers and LR in User Stack stmfd sp!, { r1-r3, r12, lr} ;- Branch to the routine pointed by the AIC_FVR mov r14, pc bx r0 ;- Restore scratch/used registers and LR from User Stack ldmia sp!, { r1-r3, r12, lr} ;- Leave Interrupts disabled and switch back in FIQ mode msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ ;- Restore the R0 ARM_MODE_SVC register mov r0,r9 ;- Restore the Program Counter using the LR_fiq directly in the PC subs pc,lr,#4 InitReset: ;------------------------------------------------------------------------------ ;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit ;------------------------------------------------------------------------------ EXTERN AT91F_LowLevelInit #define __iramend SFB(INTRAMEND_REMAP) ;- minumum C initialization ;- call AT91F_LowLevelInit( void) ldr r13,=__iramend ; temporary stack in internal RAM ;--Call Low level init function in ABSOLUTE through the Interworking ldr r0,=AT91F_LowLevelInit mov lr, pc bx r0 ;------------------------------------------------------------------------------ ;- Stack Sizes Definition ;------------------------ ;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using ;- the vectoring. This assume that the IRQ management. ;- The Interrupt Stack must be adjusted depending on the interrupt handlers. ;- Fast Interrupt not requires stack If in your application it required you must ;- be definehere. ;- The System stack size is not defined and is limited by the free internal ;- SRAM. ;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------ ;- Top of Stack Definition ;------------------------- ;- Interrupt and Supervisor Stack are located at the top of internal memory in ;- order to speed the exception handling context saving and restoring. ;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory. ;------------------------------------------------------------------------------ IRQ_STACK_SIZE EQU (2*8*4) ; 2 words per interrupt priority level ARM_MODE_FIQ EQU 0x11 ARM_MODE_IRQ EQU 0x12 ARM_MODE_SVC EQU 0x13 I_BIT EQU 0x80 F_BIT EQU 0x40 ;------------------------------------------------------------------------------ ;- Setup the stack for each mode ;------------------------------- ldr r0, =__iramend ;- Set up Fast Interrupt Mode and set FIQ Mode Stack msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT ;- Init the FIQ register ldr r8, =AT91C_BASE_AIC ;- Set up Interrupt Mode and set IRQ Mode Stack msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT mov r13, r0 ; Init stack IRQ sub r0, r0, #IRQ_STACK_SIZE ;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack msr CPSR_c, #ARM_MODE_SVC mov r13, r0 ;--------------------------------------------------------------- ; ?CSTARTUP ;--------------------------------------------------------------- EXTERN __segment_init EXTERN main ; Initialize segments. ; __segment_init is assumed to use ; instruction set and to be reachable by BL from the ICODE segment ; (it is safest to link them in segment ICODE). ldr r0,=__segment_init mov lr, pc bx r0 PUBLIC __main ?jump_to_main: ldr lr,=?call_exit ldr r0,=main __main: bx r0 ;------------------------------------------------------------------------------ ;- Loop for ever ;--------------- ;- End of application. Normally, never occur. ;- Could jump on Software Reset ( B 0x0 ). ;------------------------------------------------------------------------------ ?call_exit: End b End ;------------------------------------------------------------------------------ ;- Manage exception ;--------------- ;- This module The exception must be ensure in ARM mode ;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------ ;- Function : IRQ_Handler_Entry ;- Treatments : IRQ Controller Interrupt Handler. ;- Called Functions : AIC_IVR[interrupt] ;------------------------------------------------------------------------------ IRQ_Handler_Entry: ;- Manage Exception Entry ;- Adjust and save LR_irq in IRQ stack sub lr, lr, #4 stmfd sp!, {lr} ;- Save and r0 in IRQ stack stmfd sp!, {r0} ;- Write in the IVR to support Protect Mode ;- No effect in Normal Mode ;- De-assert the NIRQ and clear the source in Protect Mode ldr r14, =AT91C_BASE_AIC ldr r0 , [r14, #AIC_IVR] str r14, [r14, #AIC_IVR] ;- Enable Interrupt and Switch in Supervisor Mode msr CPSR_c, #ARM_MODE_SVC ;- Save scratch/used registers and LR in User Stack stmfd sp!, { r1-r3, r12, r14} ;- Branch to the routine pointed by the AIC_IVR mov r14, pc bx r0 ;- Restore scratch/used registers and LR from User Stack ldmia sp!, { r1-r3, r12, r14} ;- Disable Interrupt and switch back in IRQ mode msr CPSR_c, #I_BIT | ARM_MODE_IRQ ;- Mark the End of Interrupt on the AIC ldr r14, =AT91C_BASE_AIC str r14, [r14, #AIC_EOICR] ;- Restore SPSR_irq and r0 from IRQ stack ldmia sp!, {r0} ;- Restore adjusted LR_irq from IRQ stack directly in the PC ldmia sp!, {pc}^ ;--------------------------------------------------------------- ; ?EXEPTION_VECTOR ; This module is only linked if needed for closing files. ;--------------------------------------------------------------- PUBLIC AT91F_Default_FIQ_handler PUBLIC AT91F_Default_IRQ_handler PUBLIC AT91F_Spurious_handler CODE32 ; Always ARM mode after exeption AT91F_Default_FIQ_handler b AT91F_Default_FIQ_handler AT91F_Default_IRQ_handler b AT91F_Default_IRQ_handler AT91F_Spurious_handler b AT91F_Spurious_handler ENDMOD END Простите за длинный пост.