Средства и методы разработки

"Специалисты Cambridge Consultants создали XAP5 — 16-разрядное процессорное ядро с новой архитектурой". Похоже, успех dsPIC, PIC24 оказался заразителен. -> http://www.ixbt.com/news/all/index.shtml?10/74/67
Краткая дока на ядро http://www.cambrid …/asic/ASICs-SB-012.pdf * xIDE with GCC C compiler. * SIF serial debug interface. * Simulation can be extended using Python scripting to model other parts of an ASIC. - такое ощущение, что чуваки мои посты по синтетической отладке читали :)))) The XAP5a core, including all its registers, occupies less than 0.09 mm2 of 130 nm silicon, i.e. around 18k gates. It consumes just 27 μW per MHz of dynamic power. Но это не самое интересное. Обратите внимание на график http://www.cambrid …ltants.com/cs_xap.html 2003 год - когда был массовый психоз на тему ARM - 32 битное ядро. Далее народ занялся делом и творил только 16 битные ядра. "Rich instruction set The new XAP instruction set architecture features high code density and efficient register management using a run-time mix of 16-, 32- and sometimes 48-bit instructions. It follows contemporary thinking in instruction set design as it extends the Reduced Instruction Set Computing concept with variable length and multi-cycle instructions, whilst retaining the load-store model and a regular and orthogonal instruction set layout that is easy to understand and decode. A 16-bit XAP processor will typically halve program code size in ROM or Flash over a legacy 8- or 16-bit core, thus halving memory cost, which is particularly beneficial when programs run from on-chip memory. They will also execute programs much faster, often enabling a reduction in clock speed and therefore lower dynamic energy consumption. The XAP architecture is optimised for programming in modern languages and applications can be written entirely in C without the need for any assembly language in start-up code and interrupt service routines. Data is stored very efficiently using XAP’s unaligned memory access and byte addressing capabilities and this also makes it easier to port software originally written for other processors such as an x86. The latest XAP processors execute approximately 190 different instructions that include multi-cycle instructions for multiply, divide, shift, block-copy and store, together with special instructions to manage the stack for fast interrupt response and function entry and exit. The instructions can use zero-, register-, SP or PC-relative addressing and there are atomic instructions for single bit manipulation when reading and writing input or output port bits.Rich instruction set The new XAP instruction set architecture features high code density and efficient register management using a run-time mix of 16-, 32- and sometimes 48-bit instructions. It follows contemporary thinking in instruction set design as it extends the Reduced Instruction Set Computing concept with variable length and multi-cycle instructions, whilst retaining the load-store model and a regular and orthogonal instruction set layout that is easy to understand and decode. A 16-bit XAP processor will typically halve program code size in ROM or Flash over a legacy 8- or 16-bit core, thus halving memory cost, which is particularly beneficial when programs run from on-chip memory. They will also execute programs much faster, often enabling a reduction in clock speed and therefore lower dynamic energy consumption. The XAP architecture is optimised for programming in modern languages and applications can be written entirely in C without the need for any assembly language in start-up code and interrupt service routines. Data is stored very efficiently using XAP’s unaligned memory access and byte addressing capabilities and this also makes it easier to port software originally written for other processors such as an x86. The latest XAP processors execute approximately 190 different instructions that include multi-cycle instructions for multiply, divide, shift, block-copy and store, together with special instructions to manage the stack for fast interrupt response and function entry and exit. The instructions can use zero-, register-, SP or PC-relative addressing and there are atomic instructions for single bit manipulation when reading and writing input or output port bits." Чет мне это CF любимый напоминает. Тоже 8 регистров, переменная длина команд. Может я не прав, но мне кажется, что наступает некое отрезвление. Вкусив глюкавых АРМов, народ осознал, что размер слова не всегда имеет значение, а тупорылого программиста ARM'ом не исправишь. С другой стороны, ARM прогресс привел к массовому распространению С и RTOS (желающих кодить на ASM ARM оказалось немного). А после осознания С, RTOS и виртуальной отладки, целевая платформа становится не так критична. И часть народа, судя по всему, готова шагнуть назад, в 16 битники. В духе этой же ветви спирали и ATxmega, кстати. Если все на С, да еще на GCC, то платформа становится еще менее критична. Успевает мега - юзай ее (если набор периферии подходит), нет - бери 16 битник, нет - 32 битник, вероятно, тебе поможет. Или FPGA + контроллер. И не парься о конкретике.